Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
1999-11-02
2001-07-24
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S003000, C327S007000, C327S012000, C324S076770
Reexamination Certificate
active
06265902
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to phase detectors, and more particularly, a digital phase detector with slip detection capability for reducing phase-lock loop lock time.
BACKGROUND OF THE INVENTION
A phase-locked loop (PLL), in one form, includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) a frequency divider, and a reference frequency signal source. The PLL synthesizes a frequency source signal, for example the VCO, based on the reference frequency signal source (reference signal), for example a crystal oscillator. The phase detector keeps the frequency source and reference signals at its input equal in frequency and phase by determining a phase mismatch between the divided frequency source and reference signals, and activating the charge pump based on the amount of phase mismatch. Because of device physics, loop dynamics and system architecture, the correction cannot be made instantaneously, resulting in a finite time between the detected phase mismatch between the reference and frequency source signals and the correction of the frequency source signal. The time for the frequency source signal to achieve its intended frequency (reference frequency) is called the “lock time” of the PLL.
A digital phase detector may consist of flip-flops clocked by the edges of derivatives of the reference and frequency source signals. If one edge arrives before the other, a charge is transferred to or from a loop filter that changes the frequency of the frequency source to align the edges. The amount of charge transferred (the amount of correction) depends on the time difference between the edges of the reference and frequency source signals. However, the operating range of the digital phase detector is only −2&pgr; to 2&pgr;. An edge of the reference signal must be received for each edge of the frequency source signal for proper correction to occur. If the difference between the reference and frequency source signals is too great, two edges may appear at an input before the corresponding edge arrives at the other input. Such a situation is called a cycle slip, and leads to an improper correction, causing increased PLL lock time.
One solution to overcome the cycle slip is to extend the range of the digital phase detector. When extending the range, edges of the reference and frequency source signals are each accounted for, and as long as one input of the detector has received more edges than the other input, a correction is enabled. However, a disadvantage of simply extending the range of the phase detector is the increased overshoot in the frequency source control voltage. In voltage-limited applications, the tuning sensitivity of the voltage-controlled oscillator must be increased, resulting in higher noise, or the control voltage will reach a limit where it clips. Should the control voltage clip, the improvements in PLL lock time from using the extended range digital phase detector would be lost or even reversed.
The present invention is directed to overcoming one or more of the problems discussed above in a novel and simple manner.
SUMMARY OF THE INVENTION
In accordance with the invention, there is disclosed a digital phase detector (PD) having a slip detection circuit for detecting and compensating for a cycle slip, providing improved phase lock loop (PLL) lock time without clipping a control voltage of the voltage controlled oscillator.
In one aspect of the invention, an improved digital phase detector for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge, includes a detector circuit for detecting a cycle slip where two successive corresponding edges of one of the reference and frequency source signals are received before a respective corresponding edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to detecting a cycle slip.
In one feature of the invention, the detector circuit includes a PD for detecting a first edge of the two successive corresponding edges by detecting reception of one of a first frequency source pulse edge and a first reference signal pulse edge, and for developing a PD frequency-increase signal where the first edge is the first reference signal pulse leading edge, and developing a PD frequency-decrease signal where the first edge is the first frequency source signal pulse edge. A slip detection (SD) circuit is operatively coupled to the phase detector for receiving the reference and frequency source signals, and for detecting a second corresponding edge of the two successive corresponding edges by detecting a second corresponding reference signal edge corresponding to the first reference signal pulse edge while the frequency-increase signal is being provided, and for detecting a second corresponding frequency source pulse edge corresponding to the first frequency source pulse edge while the frequency-decrease signal is being provided. An SD frequency-increase signal is developed when the second corresponding reference signal pulse edge is detected, and an SD frequency-decrease signal is developed when the second corresponding frequency source pulse edge is detected.
In a further feature, the PD includes a pair of edge-triggered resettable flip-flops and the frequency source signal and the reference signal are clock signals for the flip-flops.
In another feature, the SD circuit includes a first counter and a second counter. The cycle slip is detected at the first counter when the second corresponding reference signal pulse edge is received at a first counter clock input while the PD frequency-increase signal is provided at a first counter comparator input, causing the first counter to load a first specified value and to provide the SD frequency-increase signal at a first counter output for the number of corresponding reference signal pulse edges equaling the first specified value. The cycle slip is detected at the second counter when the second corresponding frequency source pulse edge is received at a second counter clock input while the PD frequency-decrease signal is provided at a second counter comparator input, causing the second counter to load a second specified value and to provide the SD frequency-decrease signal at a second counter output for the number of corresponding frequency source pulse edges equaling the second specified value.
In yet a further feature, the first and second counters each have a permit load input, and including a controller coupled to the permit load inputs for allowing the first and second counters to be loaded while the respective counter is counting.
In a further feature, the first and the second counters each include a counter specified value input, and a controller coupled to the specified value inputs provides the first and second specified values.
In a further feature, the correction signal includes at least one of an output frequency-increase signal and an output frequency-decrease signal, and the output circuit includes a first OR logic gate for developing the output frequency-increase signal responsive to the PD frequency-increase signal and the SD frequency-increase signal. The output circuit also includes a second OR logic gate for developing the output frequency-decrease signal responsive to the PD frequency-decrease signal and the SD frequency-decrease signal.
In another feature of the invention, the improved digital PD includes a controller coupled to the detector circuit and the output circuit for controlling duration of the correction signal.
In yet another feature of the invention, the two successive corresponding edges of one of the reference and frequency source signals are two successive leading edges of one of the reference and frequency source, and the respective corresponding edge of the other signal is a leading edge of the other signal.
In another aspect of the invention, an im
Klemmer Nikolaus
White Steven L.
Cunningham Terry D.
Ericsson Inc.
Luu An T.
Wood Phillips VanSanten Clark & Mortimer
LandOfFree
Slip-detecting phase detector and method for improving... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Slip-detecting phase detector and method for improving..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Slip-detecting phase detector and method for improving... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2502466