Slim spacer device and manufacturing method

Details Slim spacer device and manufacturing method Slim spacer device and manufacturing method

2007-01-16

2007-01-16

Pizarro, Marcos D. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S344000, C257SE29266

Reexamination Certificate

active

10816089

ABSTRACT:
A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including at least one overlying hardmask layer; forming spacers selected from the group consisting of oxide
itride and oxide
itride oxide layers adjacent the polysilicon gate structure; removing the at least one overlying hardmask layer to expose the polysilicon gate structure; carrying out an ion implant process; carrying out at least one of a wet and dry etching process to reduce the width of the spacers; and, forming at least one dielectric layer over the polysilicon gate structure and spacers in one of tensile and compressive stress.

REFERENCES:
patent: 6046494 (2000-04-01), Brigham et al.
patent: 6140192 (2000-10-01), Huang et al.
patent: 6566254 (2003-05-01), Mikagi
patent: 6656853 (2003-12-01), Ito
patent: 6897526 (2005-05-01), Miyanaga et al.
patent: 6927117 (2005-08-01), Cabral, Jr. et al.
patent: 11233769 (1999-08-01), None

Affiliated with

Also associated with

Rating

Slim spacer device and manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Slim spacer device and manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Slim spacer device and manufacturing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3768328