Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-04-01
2004-08-03
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06771126
ABSTRACT:
TECHNICAL FIELD
This disclosure relates generally to amplifier circuits, and, more particularly, to circuits and methods for improving the slew rate of a differential amplifier circuit.
BACKGROUND
A slew rate is the maximum rate at which the output voltage of a device (e.g., an amplifier) can change. In other words, the slew rate is a measure of the ability of the device to follow its input signal. Typically, the slew rate is measured by applying a large amplitude step function to the device under test, and then measuring the slope of the output voltage waveform. The step function may be a signal starting at approximately zero (0) volt and then instantaneously rising to some large level, without overshooting or ringing, to create a step-like appearance as seen on an oscilloscope screen. The slew rate of, for example, an operational amplifier may be limited by the amplifier's frequency-compensation circuitry.
The slew rate is a parameter that can be a controlling factor in the performance characteristics of a device. A device having a low slew rate can degrade the performance and speed of a system with that device.
In
FIG. 1
, a block diagram is shown of a conventional differential amplifier
100
including a differential input stage having a P-channel transistor
110
with a gate configured to receive a first input voltage (V+) and P-channel transistor
115
with a gate configured to receive a second input voltage (V−). The sources of P-channel transistors
110
and
115
are coupled to a current source
120
that generates the current I
B
. Differential amplifier
100
also includes a load stage with an N-channel transistor
125
having a drain coupled to the drain of P-channel transistor
110
. The load stage also includes an N-channel transistor
130
with a drain coupled to the drain of P-channel transistor
115
. N-channel transistors
125
and
130
are diode-connected (i.e., the gates of transistors
125
and
130
are tied to their respective drains). The sources of N-channel transistors
125
and
130
are coupled to a first supply voltage (V
SS
) which may be a negative, positive, or ground voltage.
A P-channel transistor
135
has a source coupled to a second supply voltage V
DD
which has a higher potential than the first supply voltage (V
SS
). P-channel transistor
135
is also diode-connected (i.e., the gate of transistor
135
is tied to its drain). An N-channel transistor
140
has a drain coupled to the drain of P-channel transistor
135
, a gate coupled to the gate of N-channel transistor
130
, and a source coupled to V
SS
. A P-channel transistor
145
has a source coupled to V
DD
and a gate coupled to the gate of P-channel transistor
135
. An N-channel transistor
150
has a drain coupled to the drain of P-channel transistor
145
and to an output terminal, a gate coupled to the gate of N-channel transistor
125
, and a source coupled to V
SS
.
A capacitor
160
with capacitance (C
L
) coupled to the output terminal is the equivalent capacitance of the load which may represent a subsequent stage of the amplifier or a load external to the amplifier. The dc output voltage (V
OUT
), is expressed by equation (1):
V
OUT
=A
OL
[((
V
+)−(
V
−))−
V
OFFSET
] (1)
where V
OFFSET
is an input-referred offset voltage value, and A
OL
is the open loop gain of the amplifier
100
.
The following performance issues concern differential amplifier
100
. It is desirable to improve slew rate and settling time of differential amplifier
100
.
FIG. 2
is a waveform diagram illustrating the settling times and slew rates for an ideal output signal
200
and for a typical output signal
205
as a function of voltage (e.g., volts) versus time (e.g., micro-seconds). The settling time is defined as the time taken for the output to settle to its new value (within a certain error) when a step change in input signal occurs. For ideal output signal
200
, the settling time is zero (0) micro-second. For typical output signal
205
, the settling time
210
may be greater than zero (0) micro-second. For ideal output signal
200
, the slew rate
215
is infinite (∞) V/micro-seconds or a vertical line. For a typical output signal
205
, the slew rate
220
is typically less than infinite (∞) V/micro-seconds as shown by, for example, the sloped line
220
.
Referring again to differential amplifier
100
in
FIG. 1
, the slew rate is typically limited by the maximum current that can be driven into the output load capacitance C
L
of capacitor
160
when the inputs are skewed (one input substantially greater than the other). Assuming a current gain of &agr; from the load stage (transistors
125
and
130
) to the output stage (transistors
150
and
145
) the slew rate is given by the following equation:
Slew Rate=
I
OUT,max
/C
L
=(&agr;)
I
B
/C
L
For a given load capacitance, the slew rate can be improved by increasing the quiescent bias current, I
B
, at the expense of higher quiescent power dissipation, or by increasing a at the expense of higher power dissipation and possible stability issues. The slew rate capability of differential amplifier
100
, therefore, becomes highly constrained in low power applications where low quiescent bias currents are required, and in applications with large capacitive loads.
Amplifiers interposed between a digital-to-analog converter (“DAC”) and a panel (e.g., a flat panel display) improve the operating characteristics of display systems by isolating the panel capacitance from the DAC. Many conventional amplifier architectures, including the differential amplifier in
FIG. 1
, may employ fixed bias currents, sometimes called class-A biasing, to set the operating characteristics of some or all parts of the amplifier. While class-A amplifiers provide stable supply loading, relatively simple designs, and other benefits, their slew rate is constrained by the fixed bias currents. The constrained slew rate may be inadequate in some applications, especially those requiring low power (i.e., low bias currents) and/or high capacitive loads. Therefore, there is a need to improve the slew rate and settling time for these types of amplifiers in order to improve system performance and speed.
SUMMARY
Embodiments of systems and methods for enhancing the slew rate of a differential amplifier circuit are disclosed herein. In an exemplary embodiment, an apparatus for enhancing a slew rate of a differential amplifier comprises a gain enhancement stage coupled to a load, a current comparator coupled to the gain enhancement stage and a differential amplifier to compare a reference current value with a comparison current value, and a current mirror coupled to the current comparator and to the differential amplifier to generate a slew rate enhancement bias current to enhance the slew rate of the output voltage, wherein the comparison current value is greater the reference current value.
In another exemplary embodiment, an apparatus for enhancing a slew rate of a differential amplifier, comprising a gain enhancement stage, a load coupled to the gain enhancement stage, a current comparator coupled to the load and the gain enhancement stage, and a current mirror coupled to the current comparator, the gain enhancement stage, and the load.
Accordingly, the invention advantageously provides a circuit and method that enhance the slew rate of a differential amplifier. The invention may enhance the amplifier slew rate, while requiring less die space and/or power as compared to previous approaches for improving an amplifier slew rate. The invention may also advantageously minimize quiescent current in low power applications. The invention may also advantageously improve system performance and/or speed by providing an amplifier with an enhanced slew rate feature.
REFERENCES:
patent: 4667165 (1987-05-01), De Weck
patent: 5465054 (1995-11-01), Erhart
patent: 5471169 (1995-11-01), Dendinger
patent: 5510748 (1996-04-01), Erhart et al.
patent: 5528256 (1996-06-01), Erhart et al.
patent: 557221
Bily Stephen
Blankenship Tim
Mottola Steven J.
Winbond Electronics Corporation
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