Slew rate controller for high speed bus

Details Slew rate controller for high speed bus Slew rate controller for high speed bus

1993-08-20

1995-12-26

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327170, 327306, H03K 512

Patent

active

054791243

ABSTRACT:
A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.

REFERENCES:
patent: 4653079 (1987-03-01), Allen
patent: 4859870 (1989-08-01), Wong et al.
patent: 5111076 (1992-05-01), Tarng
patent: 5153450 (1992-10-01), Ruetz
patent: 5331217 (1994-07-01), Mellisinos
Prince, Semiconductor Memories--A handbook of Design, Manufacture, and Application, Second Edition, Chapter 8, "Trends in Static RAMs (3 pages)".
Wada et al., Simple Noise Model and Low-Noise Data-Output Buffer for Ultrahigh-Speed Memories, IEEE J. of Solid-State Circuits, vol. 25, No. 6, Dec. 1990.
Gubbels et al., A 40-ns/100-pF Low-Power Full-CMOS 256K (32KX8) SRAM, IEEE J. of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.

Affiliated with

Also associated with

Rating

Slew rate controller for high speed bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Slew rate controller for high speed bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Slew rate controller for high speed bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1371524