Slew rate controlled output buffer

Details Slew rate controlled output buffer Slew rate controlled output buffer

2005-06-07

2005-06-07

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

C327S112000

Reexamination Certificate

active

06903588

ABSTRACT:
An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

REFERENCES:
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patent: 5973512 (1999-10-01), Baker
patent: 6437622 (2002-08-01), Tinsley et al.
patent: 6617897 (2003-09-01), Lee
patent: 2002/0163360 (2002-11-01), Fifield et al.
patent: 0 479 700 (1992-04-01), None
patent: 0 678 983 (1995-10-01), None
Annex to the European Search Report on European Patent Application No. EP 04009044.1-2215.

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