Slew rate control circuit

Details Slew rate control circuit Slew rate control circuit

1993-11-08

2000-09-12

Wong, Peter S.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323275, 307110, G05F 316, H02M 318

Patent

active

061182613

ABSTRACT:
A noise limited, video, digital to analog converter having an output transition time control with multiple discrete transition times. This is accomplished by a DAC control circuit in which the slew rate of the current is controlled by providing set current levels in the inverters that drive the DAC output current switches thus limiting the current available for charging and discharging the capacitance on the nodes which control the output signal. Additional control is provided by voltage clamping of these nodes which reduces the input voltage to the analog output and results in a cleaner output waveform.
By so regulating and controlling the charging and discharging of these nodes, the variations in operation of the circuit due to the process used to produce the circuit in integrated form as well as temperature and supply voltage are further substantially reduced.

REFERENCES:
patent: 3796943 (1974-03-01), Nelson et al.
patent: 4558242 (1985-12-01), Tuthill et al.
patent: 4972136 (1990-11-01), Banura
patent: 4987324 (1991-01-01), Wong et al.
patent: 5023614 (1991-06-01), Fung et al.
patent: 5182497 (1993-01-01), Yamate et al.
patent: 5184129 (1993-02-01), Fung et al.
patent: 5237209 (1993-08-01), Brewer

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