Slew rate boost circuitry and method

Details Slew rate boost circuitry and method Slew rate boost circuitry and method

2001-02-15

2002-08-20

Shingleton, Michael B (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S257000, C330S300000

Reexamination Certificate

active

06437645

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a circuit and technique for increasing the slew rate of an operational amplifier, and also for increasing the slew rate of a differential amplifier.
The term “slew rate” of an amplifier is a measure of how fast the amplifier can charge up a large capacitor that is connected to an output conductor of the amplifier in response to a very rapid increase or decrease (such as a step function increase or decrease) of the input voltage applied to the amplifier. A high slew rate generally is a desirable characteristic of an amplifier, especially an operational amplifier, and particularly a high-speed CMOS or biCMOS operational amplifier.
The slew rate of an amplifier generally is equal the tail current used in the amplifier divided by the sum of the compensation capacitance required and the parasitic capacitance of the output transistor. One technique for increasing the slew rate of an amplifier is to increase the bias current of the input stage, but that has a tendency to increase the bandwidth of the amplifier. That leads to a need to increase the compensation capacitance of the amplifier to improve circuit stability, which tends to decrease the slew rate.
The article “A Class-AB High-Speed Low-Power Operational Amplifier in BiCMOS Technology”, by Subhajit Sen and Bosco Leung, IEEE Journal of Solid-State Circuits, Volume 31, No. 9, September 1986 describes a BiCMOS operational amplifier designed to have very high transconductance, a high slew rate, and a fast small-signal-settling response.
Prior art
FIG. 1
is a schematic diagram of an operational amplifier circuit that is very similar to one disclosed in the above Sen and Leung article. If the input voltage in− is increased, the voltages on nodes D and A also increase, because a constant current (supplied by a constant current P-channel transistor) flows through transistor Q
9
and transistor MP
22
. The increased voltage on node A turns transistor Q
1
on harder, increasing current supplied into node B, providing an increase in the slew-down rate of the output voltage vo, by turning transistors Q
6
and Q
11
on harder. Similarly, if the input voltage in+ increases, transistor Q
2
is turned on harder, and supplies additional current through transistor Q
3
and Q
5
, which turns transistor Q
7
on harder, lowering the voltage on node E and turning on transistor MP
7
harder, providing an increased slew-up current into the output conductor vo.
The circuit described has the further shortcoming of having an undesirably low commonmode rejection ratio (CMRR), an undesirably narrow power supply rejection ratio (PSRR), and an undesirably large input offset voltage. Furthermore, the noise produced by the circuit in prior art
FIG. 1
is too high for some applications.
U.S. Pat. Nos. 4,783,637, 5,512,859 and 5,510,754 disclose amplifiers designed to have high slew rates.
There has long been a need for an inexpensive, high-speed, high slew rate integrated circuit operational amplifier which has not been satisfied prior to the present invention.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a high-speed integrated circuit operational amplifier having a high common mode rejection ratio and a high slew rate.
It is another object of the invention to provide a high-speed integrated circuit operational amplifier having a high common mode rejection ratio, a high slew rate, and low noise.
It is another object of the invention to provide a differential input circuit having a high common mode rejection ratio for producing slew boost currents for output circuitry of an operational amplifier.
It is another object of the invention to provide a differential input circuit having a high common mode rejection ratio and low noise, and producing slew boost currents for output circuitry of an operational amplifier.
Briefly described, and in accordance with one embodiment thereof, the invention provides an differential input circuit (
1
) for generating slew boost currents for an output stage of an operational amplifier. In one embodiment, the invention provides a technique of operating the differential input circuit (
1
) to provide slew boost currents by providing a differential current steering circuit that includes a first transistor (M
2
) having a gate coupled to receive a first input signal (Vin−), a second transistor (M
3
) having a gate coupled to receive a second input signal Vin+, and a constant current source (
20
) coupled to sources of the first and second transistors, and providing first (
4
or
6
) and second (
5
or
7
) outputs of the differential input circuit coupled to the first (M
2
) and second (M
3
), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (
9
) coupled to the sources of the first (M
2
) and second (M
3
) transistors and the constant current source (
20
). A second slew current circuit is operated in response to the second input signal (Vin+) to produce a second slew boost current which is introduced into the current summing conductor (
9
), wherein the first and second slew boost currents boosting currents flow through the second (M
3
) and first (M
2
) transistors, respectively. The first and second output conductors are coupled to the second and first transistors so as to cause the currents flowing through the first (M
2
) and second (M
3
) transistors to flow through the first and second output conductors, respectively. In one embodiment, the drains of the first (M
2
) and second (M
3
) transistors are coupled directly to the first (
6
) and second (
7
) outputs of the differential input circuit (
1
), respectively. In another embodiment the current summing conductor (
9
) is coupled to third (
4
) and fourth (
5
) outputs of the differential input circuit (
1
) by means of third (Q
2
) third (Q
2
) and fourth (Q
3
) transistors, respectively. In another embodiment, the current summing conductor (
9
) is coupled to the first (
4
) and second (
5
) outputs of the differential input circuit (
1
) by means of third (Q
2
) and fourth (Q
3
) transistors, respectively.
In one embodiment, the differential input circuit (
1
) includes a differential current steering circuit including a first transistor (M
2
) having a gate coupled to receive a first input signal (Vin−), a second transistor (M
3
) having a gate coupled to receive a second input signal Vin+, and a constant current source (
20
) coupled to sources of the first and second transistors, the first (M
2
) and second (M
3
) transistors having drains connected to first (
6
) and second (
7
) outputs of the differential input circuit, respectively. A first slew current circuit includes a third transistor (M
1
) having a gate coupled to the gate of the first transistor (M
2
), a drain coupled to a first supply voltage conductor (GND), a fourth transistor (Q
1
) having a first electrode coupled to a source of the third transistor (M
1
), and a second electrode and a control electrode coupled to a second constant current source (
19
), and a fourth transistor (Q
2
) having a control electrode coupled to the control electrode of the third transistor (M
1
), a first electrode coupled by a first conductor (
9
) to the source of the first transistor (M
2
), and a second electrode coupled to a third output (
4
) of the differential input circuit (
1
). A second slew current circuit includes a sixth transistor (M
4
) having a gate coupled to the gate of the second transistor (M
3
), a drain coupled to the first supply voltage conductor (GND), a seventh transistor (Q
4
) having a first electrode coupled to a source of the sixth transistor (M
4
), and a second electrode and a control electrode coupled to a third constant current source (
21
), and an eighth transistor (Q
3
) having a control electrode coupled to the control electrode of the sixth transistor (M
4
), a first electrode coupled by the first conductor

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