Slew rate adjusting circuit and semiconductor device

Details Slew rate adjusting circuit and semiconductor device Slew rate adjusting circuit and semiconductor device

2001-06-04

2003-02-11

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S170000, C327S108000

Reexamination Certificate

active

06518808

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of a circuit for adjusting an output slew rate of a data output circuit. More specifically, the present invention relates to a structure for adjusting an output slew rate of a data output circuit in a clock synchronous semiconductor memory device, which in turn outputs data in synchronization with a clock signal.
2. Description of the Background Arts
In recent years, a clock synchronous semiconductor memory device, which transfers data in synchronization with a clock signal such as a system clock, has been used for transferring data fast. The clock synchronous semiconductor memory device takes in an external control signal, an address signal and write data in synchronization with a clock signal, and transfers output data in synchronization with the clock signal. Therefore, the control signal and the address signal can be taken in with only a skew of the external signals with respect to the clock signal considered, to start the internal operation at a faster timing.
Further, the data is transferred in synchronization with the clock signal. Therefore, the data transfer rate is equivalently equal to the rate of clock signal so that the data can be transferred at a high rate.
FIG. 14
schematically shows a structure of a clock synchronous semiconductor memory device in the prior art. In
FIG. 14
, the semiconductor memory device includes: an internal memory circuitry
900
which has a plurality of memory cells, and reads out data of a selected memory cell in accordance with a clock signal CLK and an output enable signal OE for producing internal read data IQ; and an output circuit
902
which externally transfers internal read data in synchronization with clock signal CLK for producing output data Q.
Internal memory circuitry
900
includes a memory cell array, a memory row select circuit, a memory cell select circuit, an internal data write circuit, an internal data read circuit, an address buffer circuit and others.
FIG. 15
is a timing chart representing a data output operation of the semiconductor memory device shown in FIG.
14
. As shown in
FIG. 15
, internal read data IQ is produced from internal memory circuitry
900
in accordance with output enable signal OE and clock signal CLK.
FIG. 15
shows internal read data IQ
0
and IQ
1
changing in synchronization with rising of clock signal CLK.
Output circuit
902
transfers internal read data IQ read from internal memory circuit
900
in synchronization with the falling of clock signal CLK. Output data Q, which is externally read out, changes in synchronization with falling of clock signal CLK. An external logic circuit such as a processor samples the received data in synchronization with the rising of dock signal CLK. The dock signal CLK is a clock signal synchronized with, e.g., an external system clock.
In
FIG. 15
, output circuit
92
is shown producing output data Q in synchronization with the falling of clock signal CLK. However, output circuit
902
may produce output data Q in synchronization with both the rising and falling edges of clock signal CLK. Further, output circuit
902
may output data Q in synchronization with the rising of clock signal CLK (internal read data IQ is transferred in synchronization with the falling of clock signal CLK).
As described above, the output data is transferred in synchronization with clock signal CLK, and a logic such as an external processor can accurately sample the data by sampling the data in synchronization with clock signal CLK, so that a memory system capable of fast data transfer can be implemented.
In the structure of the synchronous semiconductor memory device, which transfers output data Q in synchronization with clock signal CLK, output circuit
902
is required to drive the output node fast if clock signal CLK is a fast clock signal.
When a semiconductor memory device is housed in a package, a pad and a bonding wire are usually connected to an output node, and a large inductance component is present at the output node. Therefore, as shown in
FIG. 16
, when the output node is driven fast, ringing may occur. If a ringing is caused and the ringing following an overshoot at the rising of output data Q has a large amplitude, an error may occur in determination of H- and L-levels of the data. Likewise, the ringing following undershoot at the falling of data Q may cause a similar error in determination of H- and L-levels of data Q. During continuation of the above ringing, or for time periods Ta and Th, the determination of the logical level of data cannot be performed, and fast data reading cannot be performed. For preventing the above problem related to the ringing, a way of driving the output node in multiple stages has been employed to suppress the ringing conventionally, as described below.
FIG. 17
shows, by way of example, a structure of output circuit
902
shown in FIG.
14
. In
FIG. 17
, output circuit
902
includes: a transmission gate
902
a
which transmits internal read data IQ in accordance with complementary clock signals CLK and /CLK; a buffer circuit
902
b
which buffers the output signal of transmission gate
902
a
to produce a drive signal (internal data read signal) q; an N-channel MOS transistor TR
1
which discharges output node
904
to the ground voltage level in accordance with drive signal q received from buffer circuit
902
b;
a transmission gate
902
c
which passes internal read data IQ in accordance with complementary delayed clock signals CLKd and /CLKd; a buffer circuit
902
d
which buffers the output signal of transmission gate
902
c
to produce a delayed drive signal qd; and an N-channel MOS transistor TR
2
which discharges output node
904
to the ground voltage level in accordance with delayed drive signal gd received from buffer circuit
902
d.
Output node
904
is pulled up to an H-level voltage by a pull-up resistance, which is externally provided to an output signal line (output data line), but is not shown. Output circuit
902
drives output node
904
with an open drain structure.
Transmission gates
902
a
and
902
c
are rendered conductive in a same phase but in a phase-shifted timing relationship.
Each of buffer circuits
902
b
and
902
d
includes cascaded two inverter circuits, and buffers the received signal for producing drive signal q or qd. Delayed clock signal CLKd is produced by delaying clock signal CLK with a slew rate adjusting circuit, which will be described later.
FIG. 18
is a signal waveform diagram representing, by way of example, an operation of output circuit
902
shown in FIG.
17
. In the example shown in
FIG. 18
, when output circuit
902
is in the output high-impedance state, external data Q is pulled up to H-level, and internal read data IQ is at L-level in a standby state.
Internal read data IQ changes and rises to H-level in synchronization with the rising of clock signal CLK. Clock signals CLK and CLKd change in accordance with the internal clock signal when output enable signal OE is active.
When internal read data IQ rises from L-level to H-level, both clock signals CLK and CLKD are at H-level, and transmission gates
902
a
and
902
c
are both off so that output data Q is held at H-level.
When clock signal CLK falls to L-level, transmission gate
902
a
is rendered conductive, and drive signal q attains H-level in accordance with internal read data IQ so that MOS transistor TR
1
is rendered conductive to discharge output node
904
to the ground voltage level. At this time point, transmission gate
902
c
is off, and MOS transistor TR
2
maintains the off state. When a predetermined time elapses, delayed clock signal CLKd attains L-level, and transmission gate
902
c
is rendered conductive to set drive signal qd to H-level so that MOS transistor TR
2
is turned on. Responsively, output node
904
is driven by two MOS transistors TR
1
and TR
2
.
Thereafter, clock signal CLK rises to H-level, and transmission gate
902
a
is rendered non-co

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