Slew controlled frame aligner for a phase locked loop

Details Slew controlled frame aligner for a phase locked loop Slew controlled frame aligner for a phase locked loop

2000-07-20

2002-12-03

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331S016000, C375S376000, C327S156000

Reexamination Certificate

active

06489852

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed to the field of phase locked loops. More specifically, the invention provides an improved phase locked loop (“PLL”) having a slew controlled frame aligner for adjusting the feedback signal of the PLL in order to control the alignment of the PLL output with an external frame signal.
2. Description of the Related Art
Phase locked loops are well-known elements in analog and digital circuit design. A phase locked loop operates by receiving an input reference clock signal and generating a localized oscillator signal that is synchronized with the reference clock signal. The local oscillator signal that is output from the PLL may operate at the same frequency as the reference clock signal or at some integer multiple of that frequency. A general description of the theory and operational characteristics of a PLL is contained in Couch,
Digital and Analog Communication Systems
, Fourth Edition, pp. 289-296.
FIG. 1
is a circuit diagram of a known PLL circuit
10
A. This circuit
10
A includes four primary elements—a phase detector
14
, an integrator
16
, a voltage controlled oscillator (VCXO)
18
, and a counter
26
. This circuit
10
A generates a local oscillator signal (PLL clock)
34
that is synchronized with an input reference clock signal
12
, but which operates at a higher frequency than the reference clock
12
. This is accomplished by feeding back a divided down version
38
of the local oscillator signal
34
to the phase detector
14
, which then compares the phases of the reference clock signal
12
with the feedback signal
38
.
The phase detector
14
compares the phases of the signals at its two inputs, and generates output pulse signals having pulse widths that correspond to the phase difference between the two input signals. These output pulse signals are then coupled to the integrator
16
. The integrator
16
receives the pulses from the phase detector outputs and generates a voltage level at its output that is proportional to the pulse width of the phase pulses. This phase voltage is then provided as an input to the voltage controlled oscillator (VCXO)
32
.
The voltage controlled oscillator
32
generates an output clock signal, PLL clock
34
, which is characterized by a frequency that is proportional to the phase voltage from the integrator
16
. This clock signal, PLL clock
34
, is the localized oscillator signal that is synchronized with the reference clock
12
. The PLL clock signal
34
is then fed back to one of the inputs of the phase detector
14
either directly, or via a counter
26
.
The counter
26
is configured as a divide-by-N counter, and it generates the PLL feedback signal
38
, which is a frequency divided version of the PLL clock signal
34
. By selecting an appropriate value of N, a circuit designer can select the frequency of the PLL clock signal
34
with respect to the external reference clock
12
. For example, if the circuit designer desires to generate a synchronized version of the reference clock signal
12
, but at a frequency 10 times greater than the reference clock signal
12
, then the value of N would be 10.
In distributed communication systems, such as SONET/SDH networks that include a plurality of network elements coupled via fiber optic connections, there is often a need to distribute more than one reference clock to the various network elements in order to ensure synchronization of these elements. Typically, a system may include a primary input reference clock (which is used in normal operation) and a backup input reference clock (which is used when the primary clock fails.) These reference clocks are typically not synchronized to each other, but exhibit independent phase and frequency characteristics.
A PLL circuit is typically used to carry out this synchronization step. The PLL preferably locks onto the primary input reference clock. If the primary reference clock fails, however, then the PLL must lock onto the backup reference signal. But because of the independent phase and frequency characteristics of the two reference signals, this switch over often results in the PLL gaining or losing several clock cycles in comparison to other PLLs in the network that are locked onto the same reference signal.
These types of communication systems also typically distribute a unique frame signal. The frame signal is generally at a much lower frequency than either of the reference clock signals, and it is used to ensure that all of the network elements are communicating data at a common frame boundary. Thus, when the PLL switches from one reference signal to another, it must resynchronize its output with the high-frequency reference clock signal and it also must realign the same output with the distributed frame signal. This realignment step is typically carried out by adding or subtracting clock pulses to the PLL feedback signal.
FIG. 2
is a circuit diagram of a known PLL
10
B having an external frame phase detector and a single-step controller for adding or subtracting clock pulses into the PLL feedback signal. This circuit
10
B is utilized to correct the frame alignment of the PLL output when the PLL switches from a primary reference clock signal to a backup reference clock signal in order to maintain alignment with an externally-provided, distributed frame signal.
In addition to the common elements of the PLL
10
A shown in
FIG. 1
, namely the phase detector
14
, the integrator
16
, the voltage controlled oscillator
18
, and the counter
26
, the PLL
10
B shown in
FIG. 2
includes a switch
20
, a divider
24
, a frame phase detector
22
, and a single-step controller
30
. The switch
20
is coupled to the primary input reference clock
12
A and the backup input reference clock
12
B. During normal operation, the switch
20
is set to select the primary reference clock
12
A. If, however, this clock
12
A were to fail, for whatever reason, then the switch
20
is toggled to select the backup reference clock signal
12
B. The output of the switch
20
is a reference clock that is provided to one input of the phase detector
14
. Like the circuit shown in
FIG. 1
, the other input to the phase detector
14
is the PLL feedback signal
38
.
The operation of the phase detector
14
, the integrator
16
and the VCXO
18
is similar to that described above. In addition to providing the PLL output signal
34
(also referred to as the local oscillator signal) to the counter
26
, the circuit shown in
FIG. 2
also provides this signal
34
to the divider
24
. The divider divides down the frequency of the local oscillator signal
34
to generate a local frame signal
42
. The local frame signal
42
is generally characterized by a substantially lower frequency than the frequency of the local oscillator signal
34
. This local frame signal
42
is then provided to one input of a frame phase detector
22
.
The frame phase detector
22
is also coupled to an external distributed frame signal
40
, and outputs a control signal
28
that corresponds to the phase difference between the local frame signal
42
and the distributed frame signal
40
. This control signal
28
is then provided to the single step controller
30
. The single step controller
30
examines the control signal in order to determine the amount of phase lead or lag between the local frame signal
42
and the distributed frame signal
40
. Based on this determination, the single-step controller
30
then attempts to realign the two frame signals by either adding or subtracting a single clock count from the PLL feedback signal
38
. This is done by sending an “add” signal
32
or a “skip” signal
36
to the counter
26
.
When an entire clock count is added or subtracted in this manner, however, the phase detector will suddenly determine that the PLL feedback signal
38
is out of phase with the reference clock (by one clock count), and the PLL will force the VCXO to increase or decrease in frequency in order to re-lock to eliminate this phase difference.
The problem with this sudden r

Affiliated with

Also associated with

Rating

Slew controlled frame aligner for a phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Slew controlled frame aligner for a phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Slew controlled frame aligner for a phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2993861