Electrical connectors – Aligning means for dual inline package
Reexamination Certificate
2001-04-30
2003-06-17
Bradley, P. Austin (Department: 2833)
Electrical connectors
Aligning means for dual inline package
C439S607070
Reexamination Certificate
active
06579120
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a sleeve assembly for an electronic chip. More particularly, the invention relates to a sleeve assembly having a plurality of components for protecting an electronic chip from both physical and electrostatic discharge damage during storage and assisting with installation of the electronic chip.
BACKGROUND OF THE INVENTION
Electronic chips, e.g., devices fabricated for insertion into central processing units, video systems, audio systems, or the like, are widely used to perform processing operations in electronic devices. Through advances in technology, electronic chips have been manufactured in ever decreasing sizes while becoming capable of performing ever increasingly complex functions. To effectuate these functions, electronic chips are generally positioned in electrical contact with sockets, e.g., a ball grid array socket, disk socket, zero force insertion force socket, etc., positioned on substrates of the electronic devices. The electrical contacts are typically enabled by the insertion of a plurality of pins projecting from the electronic chips into a plurality of mating holes located in the sockets. In this respect, electronic chips generally possess a rather significant number of pins, e.g., on the order of about 700 pins.
In order to maintain the relatively small size of the electronic chips, while allowing for a relatively large number of pins to be situated on the electronic chips, the pins of known electronic chips are typically relatively thin and are thus susceptible to damage (i.e., the pins may be bent, broken off, or the like). This is an important factor to consider when storing the electronic chips as well as when inserting the pins of an electronic chip into the holes of a socket. For instance, when storing the electronic chips, it is often necessary to protect the pins from being bent or otherwise damaged.
Additionally, when inserting the pins into the socket holes, if the pins and the socket holes are not accurately aligned, some or all of the pins may become damaged as pressure is applied to insert the pins into the socket holes. Moreover, due to the nature of electronic chips, e.g., the rather large number of pins, a relatively significant risk of electrostatic discharge damage to the electronic chip is posed, both during storage and insertion of the chip into the socket.
It is currently relatively difficult to install known electronic chip pins into socket holes without damaging the pins. More specifically, it is often difficult for a user to see whether the pins of an electronic chip are correctly aligned with the socket holes and thus, the user may inadvertently misalign the pins with the holes thereby causing the pins to bend or otherwise become damaged as pressure is applied during insertion of the chip. Additionally, electronic chips are typically square and thus there is generally no feedback to demonstrate that the chip is correctly oriented with respect to the socket.
One solution to the problems associated with aligning the pins and the socket holes discussed above has been to provide a pair of posts on a socket to assist a user in conducting a visual check to align the electronic chip with the socket. In this type configuration, the posts may provide for vertical alignment of the pins and the socket holes, however, horizontal alignment is limited to being visually checked by a user. One drawback associated with this type of configuration is that visual alignment of the electronic chip with the socket has not proven to be sufficiently accurate to allow for the proper alignment and correct orientation cannot be determined. Instead, it has been found that even through use of this type of configuration, the pins of an electronic chip were still susceptible to damage both during installation of the electronic chip and during its storage.
SUMMARY OF THE INVENTION
According to the principles of the present invention, a sleeve assembly is provided to protect an electronic chip from physical damage as well as electrostatic discharge damage during both storage and installation of the electronic chip. In addition, with regard to the installation of the electronic chip into a socket, the sleeve assembly is configured to assist in the insertion of the electronic chip by utilizing a separate mechanical means to align and orient the electronic chip pins with the socket holes, thereby overcoming the drawbacks and disadvantages associated with known ways of aligning electronic chip pins with socket holes.
According to another aspect, the present invention pertains to a system for protecting and guiding an electronic chip into engagement with a socket. The system includes a sleeve assembly enclosing an electronic chip, in which, the sleeve assembly possesses a first sleeve member and a second sleeve member. The first sleeve member supports the electronic chip and the second sleeve member is configured to substantially reduce the electromagnetic interference of the electronic chip. The sleeve assembly is operable to assist in guiding the electronic chip into substantially proper engagement with a socket located on a substrate.
According to another aspect, the present invention pertains to a method for protecting and guiding an electronic chip on to a socket positioned on a substrate of an electronic system. According to the method, an electronic chip is inserted into a sleeve assembly possessing a first sleeve member and a second sleeve member. The sleeve assembly also possesses a plurality of substrate engaging members. In this respect the sleeve assembly functions to protect the electronic chip from physical damage.
REFERENCES:
patent: 4433886 (1984-02-01), Cassarly et al.
patent: 4506938 (1985-03-01), Madden
patent: 5241453 (1993-08-01), Bright et al.
patent: 5302853 (1994-04-01), Volz et al.
patent: 5435750 (1995-07-01), Kosmala
patent: 5735698 (1998-04-01), Bakker et al.
Bradley P. Austin
Gushi Ross
Hewlett--Packard Development Company, L.P.
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