Sleep mode refresh apparatus

Details Sleep mode refresh apparatus Sleep mode refresh apparatus

1989-11-07

1993-09-21

Rudolph, Rebecca L.

Excavating

395750, 371 163, 364DIG1, 364270, 364264, 36421691, 365227, G11C 100

Patent

active

052476553

ABSTRACT:
A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from the microprocessor to put it back into the sleep mode, thereby conserving energy. A hold signal is provided to the microprocessor to cause the microprocessor outputs to be put into a tri-state, high impedance condition, and thus relinquish control of the external bus to the external refreshing circuitry.

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