Electric power conversion systems – Current conversion – Having plural converters for single conversion
Reexamination Certificate
2002-02-08
2002-11-19
Vu, Bao (Department: 2838)
Electric power conversion systems
Current conversion
Having plural converters for single conversion
C363S131000
Reexamination Certificate
active
06483729
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to slaved supply for serial link, of master/slave type.
BACKGROUND OF THE INVENTION
Information technologies are currently exhibiting a burgeoning mode of communication between users.
Although present-day telecommunication networks allow the transmission of digital data under continually improved conditions, both as regards the bit rate and the security of transmission, the communication interfaces between the user and the machine, communication terminal, are still subject to hardware contingencies with regard to reliability, to security and the integrity of the digital data transmitted.
Such is the case in particular as regards the serial type links with which terminals playing the role of master element are equipped as are the electronic circuits of so-called peripheral elements, such as microprocessor cards, playing the role of slave element, and inserted by users into a card reader driven by the master element.
In particular, in this type of situation, the transferring of digital data from the master element to the slave element or vice-versa remains subservient, in particular, to the plurality of ohmic contacts between pins of the microprocessor card, and furthermore to the supply voltage levels applied to the master, respectively slave element.
By way of non-limiting example, the electrical diagram of the input/output buffer circuit of a mobile or non-mobile telephone supplied by a master supply circuit and the electrical diagram of a slave input/output buffer circuit, consisting of a microprocessor subscriber card for example, are supplied from a master supply voltage Vdcm, respectively from a slave supply voltage Vdce and are connected by a serial link SL.
The electrical supply to the aforesaid master and slave buffer circuits is achieved from a reference voltage Vref, delivered by a “bandgap” type circuit, which delivers a fixed voltage. This type of circuit is represented in
FIG. 1
a.
When the slave buffer circuit, the card, has to talk to the telephone, by way of the serial link SL, the telephone, playing the role of the master element, wakes up the slave buffer circuit by sending wake-up pulses. The amplitude level of these pulses is 1.8 volts, for example.
The master input/output buffer circuit is supplied from the master supply voltage Vdcm, by way of an active multiplier circuit, receiving the reference voltage Vref, a differential amplifier OPA whose positive input terminal is linked to this reference voltage forming a set-point value, a regulating transistor, playing the role of variable resistor voltage-controlled by the output of the differential amplifier OPA. This regulating transistor is connected between the master supply voltage Vdcm and a master regulated supply voltage output point, a smoothing capacitor connected between the output point of the master regulated supply voltage and the earth voltage of the device of the master element and a divider point R
1
, R
2
linking the output point of the master regulated supply voltage to the negative input of the differential amplifier. For a given ratio of resistances R
1
, R
2
, an output value of master regulated supply voltage which is lower than the value of the master supply voltage Vdcm but greater than the value of the reference voltage Vref is obtained at equilibrium.
Typically, for a reference voltage Vref=1.25 volts, an output value of regulated supply voltage of 1.8 volts supplying the master input/output buffer circuit is obtained.
Under the normal operating conditions, in the presence of good ohmic contacts, provided however that the master reference voltage VREF and the slave reference voltage Vref, the master and slave resistances R
1
respectively R
2
are equal and hence that the peak value of the master digital output signals is identical to the slave regulated supply voltage, such a mode of operation guarantees master respectively slave digital input/output signals of substantially the same peak value and the same amplitude.
However, by reason of an inbalance in the equilibrium of the voltage ratios VREF/Vref and of the master and slave resistances R
1
or R
2
, the aforesaid normal conditions are not always obtained, thereby giving rise to a degradation of the peak value and of the amplitude of the digital input/output signals of the master, respectively slave buffer circuits. Furthermore, when the master respectively slave supply voltage values are distinct and different, the risk of mismatch of the amplitude of the digital input/output signals of the aforesaid buffer circuits is increased, a risk of increased consumption and of destruction of the slave supply circuits through the so-called “latch-up start” phenomenon corresponding to a latching of inrush current liable to destroy the bipolar transistors. These risks are illustrated in
FIG. 1
b.
SUMMARY OF THE INVENTION
The object of the present invention is to remedy the aforesaid drawbacks of the circuits of the prior art, through the implementation of a circuit for regulating the supply of a slave element linked to a master element by a serial link, this regulating circuit making it possible to slave the slaved regulated slave supply voltage to the peak value of the master digital output signals, thereby making it possible to eliminate any risk of degradation or of destruction of the slave circuits and moreover to adapt automatically to any type of telephone 1.8 V; 2.7 V; 3.3 V without changing the slave circuit.
Another object of the present invention is also, on account of the aforesaid slaving of the slave regulated supply voltage to the peak value of the master digital output signals, the implementation of a slave regulated supply circuit of substantially simplified structure, in which any reference voltage generator of “bandgap” type is eliminated.
The slaved supply for linking a slave element linked to a master element by a serial link that is the subject of the present invention is formed by a master element comprising a master module for regulating the electrical supply voltage of a master output circuit delivering master digital output signals and by a master input circuit, receiving slave digital output signals by way of this serial link. The slave element comprises, supplied by a slave electrical supply voltage, a slave input circuit receiving the master digital output signals by way of this serial link. A slave output circuit delivers the slave digital output signals and a slave module for regulating the electrical supply voltage of the slave input and output circuits is provided.
The slave module for regulating the electrical supply voltage comprises, on the one hand, a module for sampling and for detecting the peak value of the master digital output signals received by way of the serial link, this sampling and detecting module delivering a sampled peak value of the master digital output signals, and, on the other hand, a slaving module tracking the slave supply voltage of the slave input and output circuits to a value substantially equal to that of the sampled peak value of the master output signals. The slave module for regulating the electrical supply voltage makes it possible to deliver slave digital output signals whose peak amplitude is substantially matched to the peak amplitude of the master digital output signals.
The slaved supply and the slave module for regulating the supply voltage, which are the subjects of the present invention, find application to the embodying of electrical supply circuits of telecommunication equipment such as mobile or fixed telephones and their equipment microprocessor cards, in the form of CMOS type integrated circuits.
REFERENCES:
patent: 5097183 (1992-03-01), Vila-Masot et al.
patent: 5289176 (1994-02-01), Novakovich et al.
patent: 5313143 (1994-05-01), Vila-Mascot
patent: 5490117 (1996-02-01), Enzo et al.
patent: 5623224 (1997-04-01), Yamasa et al.
patent: 5929616 (1999-07-01), Perraud et al.
patent: 6345187 (2002-02-01), Berthoud et al.
patent: 6346798 (2002-02-01), Passoni et al.
Atmel Nantes S.A.
Kenaga Michael L.
Piper Rudnick
Vu Bao
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