Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1998-02-19
2001-03-27
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S194000
Reexamination Certificate
active
06208548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a select circuit for selecting a circuit in a specific portion of a system formed of electronic circuits.
2. Description of the Background Art
Some of systems formed of electronic circuits operate in such a manner that a specific device (e.g., a bus master circuit such as a CPU) selects one of a plurality of devices (e.g., slave circuits such as memories) with a select circuit for input/output of data through a data bus.
FIG. 6
is a schematic block diagram showing a system which employs a conventional select circuit and is formed of a master circuit such as a CPU or the like and slave circuits such as dynamic semiconductor memory devices which will be referred to as “DRAMs”, or static semiconductor memory devices which will be referred to as “SRAMS” hereinafter.
Referring to
FIG. 6
, a chip
0
which is a chip of a bus master carries a CPU issues onto a select signal line CM a signal specifying a chip to be selected among chips
1
-
3
of slave circuits, and transmits data to and from chips
1
-
3
through a data bus BUS.
Chips
1
-
3
which are slave chips formed of DRAMs or SRAMs output or input data onto or from data bus BUS through data I/O terminals DQc
1
-DQc
3
when corresponding chip enable signal input terminals CE
1
-CE
3
receive active signals at “H” level, respectively.
A select signal generating circuit S
1
activates (i.e., sets to “H” level) one of chip select signals CS
1
-CS
3
, which are applied to chips
1
-
3
of the slave chips, respectively, in response to a signal sent from chip
0
of the master circuit through select signal line CM.
An operation in which chip
0
of the master chip receives data from chip
3
of the slave chip will now be described as an example of the operation of the structure shown in FIG.
6
.
FIG. 7
is a timing chart showing the above operation.
Chip
0
of the bus master sends to select signal generating circuit S
1
a signal instructing it to activate chip select signal CS
3
to attain “H” level.
Select signal generating circuit S
1
sets signal CS
3
to the active state (“H” level) in response to the signal sent from chip
0
of the bus master at time &tgr;
0
.
Due to delay on a signal interconnection, the potential level on chip enable signal input terminal CE
3
of chip
3
of the slave chip (i.e., the potential level on a node P
3
of the signal interconnection) attains the active state (“H” level) after a time period of 3×&tgr;
0
from time t
0
. Chip
3
of the slave chip sends the data to data I/O terminal DQc
3
at time t
2
after a constant time period, which is assumed to be equal to &tgr;
0
for simplicity reason, from activation of the potential level on chip enable signal input terminal CE
3
.
In the following description, it is assumed that the chips
1
-
3
of the slave chips continuously issue nine data with a cycle time of &tgr;
0
.
At time t
3
after a time period of 3&tgr;
0
from time t
2
, chip
0
of the bus master receives through data bus BUS the data, which is sent from chip
3
of the slave chip and takes the form of change in potential on node DQ
0
between data bus BUS and chip
0
.
Description will be further given on the case that bus master chip
0
receives the data from chip
1
of the slave chip subsequently to start of reception of the data from chip
3
of the slave chip at time t
3
.
Chip
0
of the bus master issues to select signal generating circuit S
1
signal CM instructing deactivation (“L” level) of signal CS
3
after a time period of 9×&tgr;
0
from issuance of the instruction for setting signal CS
3
to the active state (“H” level).
At the same time, chip
0
of the bus master sends signal CM instructing activation (“H” level) of signal CS
1
to select signal generating circuit S
1
.
Select signal generating circuit S
1
keeps signal CS
3
in the active state (“H” level) for a time period of 9×&tgr;
0
from time t
0
to time t
4
in accordance with the signal sent from chip
0
of the bus master, and subsequently keeps signal CS
1
in the active state (“H” level) for a time period of 9×&tgr;
0
from time t
4
to time t
8
.
Due to an interconnection delay, the potential level on chip enable signal input terminal CE
3
of chip
3
of the slave chip (i.e., potential level on node P
3
) attains the inactive state (“L” level) at time t
7
after a time period of 3×&tgr;
0
from time t
4
. The potential level on chip enable signal input terminal CE
1
of chip
1
of the slave chip (i.e., potential level on node P
1
) attains the active state (“H” level) at time t
5
after a time period of &tgr;
0
from time t
4
.
Further, chip
1
issues the data to data I/O terminal DQc
1
at time t
6
after a time period of &tgr;
0
from time t
5
.
As described above, chip
0
of the bus master receives the data issued from chip
3
through data bus BUS when a time period of 3×&tgr;
0
elapses after chip
3
starts output of the data. Chip
0
of the bus master receives the data when a time period of &tgr;
0
elapses after chip
1
of the slave chip starts output of the data.
However, chip
1
of the slave chip is located near bus master chip
0
so that the data sent from chip
1
of the slave chip arrives at chip
0
of the bus master in a shorter time than the data from the other slave chips. This may results in such a problem that the data sent from chip
1
of the slave chip arrives at the bus master while chip
0
of the bus master is receiving the data sent from chip
3
forming the slave ship, and therefore collision of data occurs.
For avoiding the above data collision, Japanese Patent Laying-Open No. 5-250280 (1993) has disclosed a structure in which output of data from slave chips starts in response to a start signal sent through a path of which is folded at a chip remotest from the bus master.
According to this structure, however, one start signal is supplied to all the slave chips, and the slave chips output the data after individually determined delay times, respectively. Therefore, one start signal operates to read or write the data from or into all the slave chips so that it is impossible to select one of the slave chips for reading or writing the data.
SUMMARY OF THE INVENTION
An object of the invention is to provide a select circuit for a system in which a master circuit transmits data to and from a plurality of slave circuits, and particularly the select circuit which can avoid collision of data sent from the slave circuits even when selection of arbitrary one of the slave circuits is performed successively.
Another object of the invention is to provide a select circuit which can be used for transmission of data by a master circuit with respect to a plurality of slave circuits, and can perform selection of slave circuits with a simple structure without increasing the number of buses for selecting the slave circuits.
In summary, the invention provides a slave circuit select device including a select signal generating circuit, a signal interconnection and select circuits.
The select signal generating circuit issues a select signal including two pulse signals in response to a control signal sent from a master circuit. The signal interconnection is divided into first and second interconnection portions, and is folded at a boundary between the first and second interconnection portions. The select circuits are provided correspondingly to a plurality of slave circuits to be selected in accordance with a signal transmitted through the signal interconnection, respectively, and are arranged at corresponding positions on the signal interconnection, respectively.
For selecting the slave circuit corresponding to the specific select circuit, the select signal generating circuit issues the two pulse signals to one end of the signal interconnection such that a time interval between the two pulse signals corresponds to a delay time in transmission of the pulse signal from the specific select circuit to the specific select circuit through the first interconnection portion, the b
Hoang Huan
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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