Skipped carry incrementer for FFT address generation

Details Skipped carry incrementer for FFT address generation Skipped carry incrementer for FFT address generation

2005-12-13

2005-12-13

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S672000

Reexamination Certificate

active

06976047

ABSTRACT:
A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to the binary word, and skipping a carry bit as selected by a one-hot decoded stage value during the addition operation. The apparatus includes consecutive adders configured to store a binary value and perform an addition operation on the binary value, multiplexers configured to select either the carry out output of the current consecutive half adder or the carry out output of the previous consecutive half adder as the carry in input of a next consecutive adder, and sets of logic gates that provide one bit of the data address.

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