Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-01-31
2001-10-30
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S148000, C341S150000, C341S152000, C341S131000, C341S136000
Reexamination Certificate
active
06310569
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to differential switching schemes for current-mode digital-to-analog converters (DACs).
BACKGROUND OF THE INVENTION
Digital-to-analog converters mainly designed for video applications have a very poor spectral purity when used in communication applications such as the transmit portion of wired and/or wireless digital communication systems. Delay differences between when a bit turns on and when it turns off results in a shift from the ideal fifty percent duty cycle (square wave) and leads to even-order harmonics in the output spectrum. For a given delay difference or skew in time (when a bit turns off or on), the higher the output frequency, the more pronounced the distortion. A typical prior art CMOS current-mode DAC switching scheme, shown in
FIG. 1A
, includes transistors
20
and
22
; current source
24
; input nodes Q and QB; and output nodes
26
and
28
. In the circuit of
FIG. 1
, the time skew between Q and QB is of major concern for communication applications. The switches (transistors)
20
and
22
are like a differential pair. The prior art circuit of
FIG. 1
uses PMOS transistors, but the same problems with time skew also exist when NMOS switches and current sources are used.
Individual current sources in current mode digital-to-analog converters (DACs) use differential switches to steer current through either one of the two switches. The above mentioned differential switches are controlled by two digital complementary control signals, Q and QB, where, if Q=VDD (power of the highest potential), then QB=VSS (ground or the lowest potential) and vice-versa. Due to the physics of the inverting circuit, there is always some time delay or skew between the original signal and its inverted counterpart. Normally, QB is derived by inverting Q, as shown in
FIG. 1B
, and thus, there is always some skew present between Q and QB. When current mode DACs are used in frequency domain applications, such as communications systems, the skew between, Q and QB introduces both harmonic and non-harmonic related distortion in the spectrum of the output signal. Hence, the spurious-free dynamic range (SFDR) of the DAC is greatly reduced.
Some attempts have been made in the prior art to improve the time skew problems described above. One example is U.S. Pat. No. 5,689,257 “Skewless Differential Switch and DAC Employing the Same”, Nov. 18, 1997. In this patent, two cross-coupled inverters
29
and
30
, as shown in
FIG. 1C
, are used to minimize the skew. However, this technique is limited by mismatches between the two inverters.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, the differential switching circuit includes: a first inverter; a first pull-up transistor coupled between the first inverter and a high-side power supply node; a first pull-down transistor coupled between the first inverter and a low-side power supply node; an output node of the first inverter coupled to a control node of the first pull-up transistor and a control node of the first pull-down transistor; a second inverter; a second pull-up transistor coupled between the second inverter and the high-side power supply node; a second pull-down transistor coupled between the second inverter and the low-side power supply node; and an output node of the second inverter coupled to a control node of the second pull-up transistor and a control node of the second pull-down transistor, wherein the first and second inverters are coupled together between the inverters and the pull-up transistors, and between the inverters and the pull-down transistors.
REFERENCES:
patent: 5450084 (1995-09-01), Mercer
patent: 5612697 (1997-03-01), Mercer
patent: 5689257 (1997-11-01), Mercer et al.
patent: 6031477 (2000-02-01), Mercer
patent: 6100830 (2000-08-01), Dedic
Douglas Mercer, “A 16-b D/A Converter with Increased Spurious Free Dynamic Range” IEEE Journal of Solid-State Circuits, vol. 29, No. 10, pp. 1180-1185, Oct. 1994.
Douglas Mercer et al., “12-b 125 MSPS CMOS D/A Designed for Spectral Performance” pp. 243-246, 1996.
Bellaouar Abdellatif
Chaudhry Irfan A.
Fares Mounir
Soenen Eric G.
Brady III Wade James
Mai Lam T.
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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