Skewless differential switch and DAC employing the same

Details Skewless differential switch and DAC employing the same Skewless differential switch and DAC employing the same

1999-11-16

2002-04-02

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S144000, C327S051000

Reissue Patent

active

RE037619

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of differential switches and, in particular, to differential switches operated under control of a single binary signal, as in the case of digital to analog converters (DACs).
2. Description of the Related Art
Binary-control differential switches operate as single-pole double-throw switches and are employed in many applications such as DACs. Within such a switch, a single control terminal effects contact between a first conducting terminal and a second conducting terminal while breaking contact between the first conducting terminal and a third conducting terminal. Although the utility of such switches will be described in reference to their application within DACs, they may be used for many other applications.
There are a number of conventional DAC architectures which employ differential switches. Some are current output, some are voltage output. For examples of both see,
Analog
-
Digital Conversion Handbook,
Daniel H. Sheingold ed., Prentice Hall, Englewood Cliffs, N.J., 1986, pages 191-206. A current output DAC is illustrated in
FIG. 1
, but the new switches are applicable to voltage output DACs as well. Generally, a DAC is a device which converts a quantity specified as a binary number (this includes BCD, two's complement and other binary codes) into a current or voltage which is proportional to the value of the digital input. The digital input is typically held in a digital section
11
which may receive the digital input either serially or in parallel through a digital interface
13
. The binary number thus stored typically controls an analog output section
15
which comprises a set of differential switches S
1
-Sn, with each bit of the binary number controlling which one of two terminals within an associated differential switch S
1
-Sn is connected to a third terminal within the switch. In some cases a single switch is employed to “build up” an analog signal over some period of time.
More specifically, in the design of
FIG. 1
, an array of differential switches S
1
-Sn connect binarily-weighted current sources I
1
-In to either a return, or reference, terminal
10
or output terminal
12
under control, respectively, of binary control inputs from the least significant bit LSB
14
to the most significant bit MSB
18
. Current for the sources I
1
-In is provided through terminal
9
. The sum of the currents appearing at the output terminal
12
provide a “stair step” approximation to the continuous signal represented by the binary control inputs MSB-LSB. Alternatively, the reference terminal
10
and output terminal
12
could be connected to high and low voltage references and the terminal
9
would then provide a voltage output. In this case, the taps of a resistor ladder are connected in place of the current sources I
1
-In.
As the binary values at the control inputs LSB-MSB vary, the switches S
1
-Sn route currents corresponding to the varying binary values of the control inputs to the output terminal, where the total current may be converted into a voltage. The switches are generally switched “simultaneously” to provide valid current levels at the output terminal
12
. However, as will be explained in greater detail in relation to
FIG. 2
, there is often a delay introduced between the “make” and “break” actions of the switches S
1
-Sn, causing spurious signals, or “glitches”, to appear at the output terminal
12
.
The mid-scale glitch, produced by the transition of the control codes appearing at terminals
18
-
14
between 1000 . . . 0 and 0111 . . . 1, is usually the worst glitch because all the switches S
1
-Sn are switching at this transition. Glitches will also occur at other transition points, but they will generally be of lesser magnitude. Glitches are particularly onerous in waveform reconstruction applications such as direct digital synthesis systems.
Code-dependent glitches, such as those just discussed, will produce both out-of-band and in-band harmonics of the desired signal. For example, in reconstructing a sine wave, the midscale glitch occurs twice during each sine wave period, at each mid-scale crossing. In this manner the midscale glitches produce a second harmonic of the sinewave. Although filtering may eliminate or reduce to a tolerable level the contribution from some of the glitches, higher order harmonics, which alias back into the Nyquist bandwidth, cannot be filtered. To avoid filtering and to eliminate spurious signals that cannot be filtered, it would therefore be desirable to avoid introducing the glitches whenever possible.
The block diagram of
FIG. 2A
provides a more detailed view of a typical conventional switch, which may be employed as one of switches S
1
-Sn of FIG.
1
. As an example, switch S
1
includes a differential switch pair
20
, comprising switches swa and swb, which connect either terminal a or b to terminal c. Control terminals T and I are connected to receive complementary control signals developed within a latch L
1
. The latch L
1
accepts the binary control signal MSB and converts it into a complementary pair of control signals for use with the differential pair swa and swb. The utility of the latch L
1
derives from the fact that, at a system level, whatever device is driving, or controlling, the DAC, in all probability has other duties to perform and may address those other duties only if it stores its required digital patterns within the switches S
1
-Sn, and then proceeds to other operations.
The control input MSB provides a digital signal path for control inputs to the switch S
1
. An MSB signal enters the latch L
1
and, under control of enable signals ck and ckb, is transferred through an analog switch ASW
1
. It is then inverted, or complemented, by an inverter INV
1
to produce a control signal INVERTED which is applied to the control terminal of the switch swb. Analog switches are known in the art. A description of them may be found in, Paul Horowitz, and Winfield Hill,
The Art of Electronics,
Cambridge University Press, N. Y., 1989, pages 142-143. The output of the inverter INV
1
is connected to the input of a second inverter INV
2
which inverts the signal INVERTED to produce a control signal TRUE which is applied to the control input
24
of the switch swb, the other switch of the differential pair. Note that inversion of the INVERTED signal by inverter INV
2
produces a delay between the control signals applied to the differential pair. That is, the INVERTED signal will arrive at the control terminal
22
of switch swb one inverter's delay before the TRUE signal arrives at the control terminal
24
of switch swa. Consequently, a glitch impulse will be created at the S
1
output terminal c.
Returning to the operation of the latch L
1
, the enable signals ck and ckb are assumed to be complementary and non-overlapping. That is, more circuitry than a simple inverter is required to produce ckb from ck. During a first phase of the enable signals ck and ckb, the input signal from MSB is “clocked” through the analog switch ASW
1
. At the same time, because the control inputs to analog switch ASW
2
are connected opposite to the connection of ASW
1
, ASW
2
will be “off”, thus isolating the output of ASW
1
from the output of the inverter INV
2
.
However, during the second phase of the enable signals, analog switch ASW
1
is off and ASW
2
is on. With ASW
1
off, the MSB terminal is isolated from the circuit beyond the analog switch ASW
1
. With analog switch ASW
2
on, inverters INV
1
and INV
2
are “cross-coupled”. That is, the output of INV
1
feeds the input of INV
2
and the output of INV
2
feeds the input of INV
1
. In this conventional configuration, there are two stable states which the inverters may assume, i.e., INV
1
=1, INV
2
=0 or INV
1
=0, INV
2
=1 and, by feedback, they will remain in whichever state to which they are forced. In this way the cross-coupled inverters, coupled through the switches ASW
1
and ASW
2
, form a latch which provides TRUE(delayed) and INVE

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