Skew-free clock signal distribution network in a microprocessor

Details Skew-free clock signal distribution network in a microprocessor Skew-free clock signal distribution network in a microprocessor

1993-02-22

1995-03-14

Chin, Stephen

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

375230, 375376, 333 18, 327258, 327292, H04L 700, H03D 324

Patent

active

053982622

ABSTRACT:
A clock signal distribution network in a microprocessor of a computer system for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal. A clock driver drives the global clock signal to the plurality of units. An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units. A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time. Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver. A dummy buffer introduces the input delay of the clock generator to the global clock signal. The phase locked loop circuit controls the generation of the controllable delay to the first clock signal in response to the output signal from the dummy buffer such that the global signal received at each of the plurality of units is synchronized to the clock input signal independent of a process variation, a temperature variation, and a voltage supply variation.

REFERENCES:
patent: 3725793 (1973-03-01), Phillips
patent: 3921079 (1975-11-01), Heffner et al.
patent: 4805095 (1989-02-01), Armstrong et al.
patent: 5053649 (1991-10-01), Johnson
patent: 5059818 (1991-10-01), Witt et al.

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