Skew cancellation for source synchronous clock and data signals

Details Skew cancellation for source synchronous clock and data signals Skew cancellation for source synchronous clock and data signals

2007-11-27

2007-11-27

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S355000, C375S371000, C327S161000

Reexamination Certificate

active

10447120

ABSTRACT:
The skew between a received clock signal and a received data signal that are source synchronous, is accounted for such that stable bit values of the received data signal may be sampled. For programmable skew cancellation, a skew value corresponding to the amount of the skew is determined and programmed into a data storage device. Sampling clock signals of the same frequency but different phases are generated from the clock signal, and one of the sampling clock signals having the desired phase is selected depending on the programmed skew value. Alternatively, for automatic skew cancellation, a phase locked loop compares the received data signal to one of the sampling clock signals to determine the skew value for selecting the sampling clock signal having the desired phase. Stable bit values of the data signal are then sampled with the selected sampling clock signal.

REFERENCES:
patent: 6031428 (2000-02-01), Hill
patent: 6650575 (2003-11-01), Khanna
patent: 7031420 (2006-04-01), Jenkins et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
Jason Konstas.,Converting Wide, Parallel Data Buses to High Speed Serial Links, International IC Conference Proceedings, 1999, pp. 19-30.
National Semiconductor Corporation Data Sheet,48-Bit LVDS Channel Link Serializer/Deserializer, Jul. 2000, pp. 1-17.

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