Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2002-03-19
2004-10-19
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S119000
Reexamination Certificate
active
06806748
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims priority from prior French Patent Application No. 01 03794, filed on Mar. 21, 2001, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sinusoidal signal multiplier circuit. The invention can be applied, for example, in the field of analog FM demodulators.
2. Description of the Related Art
The multiplier circuits commonly used to multiply sinusoidal signals are asymmetrical cells showing a phase shift between their inputs. An asymmetrical multiplication cell may be modelled in the form of a perfect, two-input multiplier circuit having, at each of its inputs, an element that introduces a phase delay. A modelling of this kind is shown in FIG.
1
. The multiplication cell, referenced C, has two inputs E
1
and E
2
receiving sinusoidal signals, S
1
(t) and S
2
(t), and one output S delivering a sinusoidal signal O(t). In this cell, the input signals S
1
(t) and S
2
(t) are phase-shifted by phase delay elements, respectively introducing a phase delay (&phgr;
1
and &phgr;
2
, and are then multiplied by a perfect multiplier. If the inputs E
1
and E
2
of the multiplication cell respectively are provided with the signals S
1
(t)=A
1
*cos(wt) and S
2
(t)=A
2
*sin(wt), the following signal O(t) is obtained at the output of the multiplication cell:
O
(
t
)
=
A
1
A
2
*
cos
(
w
t
-
ϕ
1
)
*
sin
(
w
t
-
ϕ
2
)
=
(
A
1
A
2
/
2
)
*
sin
(
2
w
t
-
ϕ
1
-
ϕ
2
)
+
(
A
1
A
2
/
2
)
*
sin
(
ϕ
1
-
ϕ
2
)
The output signal O(t) comprises a sinusoidal component (A
1
A
2
/2)*sin(2wt−&phgr;
1
−&phgr;
2
) and a DC component (A
1
A
2
/2)*sin(&phgr;
1
−&phgr;
2
) corresponding to an amplitude offset of the output signal. This additional DC component in the output signal O(t) is undesirable for many applications.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
SUMMARY OF THE INVENTION
It is an aim of the present invention to provide a multiplier circuit capable of delivering an output signal substantially without any DC component.
An aspect of the present invention therefore is a sinusoidal signal multiplier circuit capable of producing an output sinusoidal signal substantially without any DC component, comprising a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input, the first multiplication cell delivering a first output signal, and the sinusoidal signal multiplier circuit furthermore comprising: a second multiplication cell identical to the first multiplication cell receiving the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivering a second output signal, and an adder circuit to add the first output signal and the second output signal in order to generate from the sinusoidal signal multiplier circuit an output signal that is substantially without any DC component.
REFERENCES:
patent: 4499426 (1985-02-01), Parker
patent: 5648736 (1997-07-01), Ishigaki
patent: 5883548 (1999-03-01), Assard et al.
patent: 6417712 (2002-07-01), Beards et al.
patent: 3138464 (1983-04-01), None
patent: 0370539 (1990-05-01), None
patent: 0574083 (1993-12-01), None
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Gutman Jose
Jorgenson Lisa K.
Nguyen Linh M.
STMicroelectronics S.A.
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