Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-05-20
2001-02-06
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S184000, C327S291000, C327S565000, C333S109000, C333S238000, C333S001000
Reexamination Certificate
active
06184736
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a digital computer, and more particularly to the distribution of clock signals for timing and synchronizing devices of the computer that are interconnected by a common, high-speed, synchronous, bidirectional bus.
BACKGROUND OF THE INVENTION
A conventional digital computer includes various components or “modules,” such as a central processing unit (“CPU”), main memories, and an input/output (“I/O”) unit, which are all interconnected for transferring signals therebetween by a common bus. For synchronous operation, the computer modules receive clock signals to control the timing of their operations. The clock signals synchronize, for example, the transfer and reception of data and other signals between the computer modules.
The computer typically employs digital clock signals, i.e., trains of rectangular pulses. The digital clock signals are characterized by a pulse rate or periodicity at the desired clock frequency of, e.g., about 58 mega-Hertz (“MHz”). Typically, at such radio-frequencies, the pulses have rapid rise times in the nanosecond range.
For proper operation of the computer, the clock signal received by each module should have the same phase as that of each of the other clock signals received by the other modules, and should not have significant levels of distortion (e.g., wave shape distortion). A phase difference in the received clock signals is called “clock skew.” Where clock skew is present, modules on the bus can require corresponding additional time to latch onto data and other signals sent over the bus, thus decreasing the maximum bus speed. Extreme levels of clock skew can have even more pernicious effects on computer performance; for example, system components may be unable to receive and decode data and other signals sent over the bus.
To ensure that the clock signals have as nearly identical phases as possible at the respective modules, the computer typically generates the clock signals centrally and distributes them over clock lines of the bus to receiver circuits of the computer modules. In each clock receiver circuit, the incoming clock signal is amplified, any distortion in the rectangular shape of the pulses is removed, and the clock signals are replicated into multiple copies for use by various circuits within the module.
Generally speaking, known high-performance clock generating systems that distribute multiple clock signals to computer modules for precise synchronization of their operation use time-delay adjustments to compensate for clock skew at the receiver ends of the system. The use of such time-delay adjustments can be costly in terms of design, implementation, and overhead. Moreover, clock skew can be difficult to predict, and therefore it is difficult to provide the proper amount of time-delay adjustment at the receiver end.
Accordingly, it would be desirable to provide a technique for preventing the introduction of clock skew in the first place, i.e., during the generation and distribution of the clock signals.
SUMMARY OF THE INVENTION
The invention resides in a clock generation system of a digital computer, which generates radio-frequency sinusoidal signals that are distributed over dedicated clock lines to clock-users, i.e., the components or modules within the computer. Also, the clock lines are configured and shielded in a novel manner so as to provide the same overall propagation rates for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference, thus reducing both clock skew and distortion. The clock signals provided by the invention do not require time-delay adjustments at the clock receivers in most applications to compensate for clock skew originating in the clock generation system.
The invention permits the generation of clock signals at, e.g., about 58 MHz, having minimal clock skews, e.g., on the order of 50 to 100 picoseconds, which is an order of magnitude lower than the two to three nanosecond skews of clock signals in known prior art clock distribution systems.
More specifically, the clock generation system of the invention includes a clock generation module, a distribution system, and receiver circuits in clock-user modules, which are preferably implemented on a single printed circuit board (the “mother board”) of the computer.
The clock generation module includes an oscillator for generating a sinusoidal signal at a pre-selected clock frequency, which typically contains harmonics thereof; a low-pass filter for filtering the sinusoidal signal to substantially attenuate the harmonics; and a signal splitting circuit for generating copies of the filtered sinusoidal signals, the copies also being sinusoidal in nature. In a preferred implementation, the signal splitting circuit includes both a phase splitter for generating quadrature-related clock signals, and signal splitters for providing multiple copies of those clock signals. Other applications that do not require quadrature-related clock signals can eliminate the phase splitter.
The distribution system includes the shielded clock lines of a synchronous bus, which distribute the sinusoidal clock signals to the clock-user modules. The clock lines have the same overall dimensions, including lengths (i.e., distances between the clock generation module and each clock-user module), material, and signal propagation characteristics.
Each clock-user-module receiver circuit is preferably implemented on a single integrated-circuit chip, and serves to convert at least one of the sinusoidal clock signals into a digital clock signal for use by the module. Where quadrature-related sinusoidal clock signals are distributed to the modules, the receiver circuit converts both those sinusoidal signals into quadrature-related digital clock signals.
In accordance with another aspect of the invention, each clock line is shielded against cross-talk and radio-frequency, electromagnetic radiation by a strip-line arrangement that surrounds each clock line. The strip-line arrangement includes conductive planes and conductive vias (i.e., plated through-holes) provided in the mother board and the modules. Specifically, each clock line is disposed between and isolated from top and bottom conductive planes, and flanked by and isolated from spac conductive vias that interconnect the conductive planes The spacing between the conductive vias is approximatel {fraction (1/10)} of the smallest wavelength of the radiation agains which the clock lines is shielded. For instance, this distance is about 0.2 to 0.3 inches (0.5 to 0.76 cm) fc isolating against signals having frequencies less than about two gigahertz.
This arrangement effectively blocks both cross-talk between clock lines and electromagnetic interference from other sources. In addition, this arrangement blocks the emmission of electromagnetic radiation from the clock lines, which is frequently desirable to prevent signal interference in other computer components and to comply with applicable governmental standards.
This invention is based on the recognition that.prior art clock distribution arrangements often introduced unacceptable levels of clock skew and distortion because of signal propagation rate variations between the clock lines of the synchronous buses used to distribute the clock signals. Propagation rates in these lines are frequency dependent.
Even though only a single clock frequency may be desired, the clock lines of prior art systems carry signals at various other frequencies. Specifically, these are mainly the multiple harmonics of the clock frequency, which can be found in the digital clock signals. The range and magnitude of the harmonics in the prior art clock signals are due to the rapid rise and fall times of the pulses in these signals. Other unwanted components in the clock signals may be produced by cross-talk from other bus lines, and electromagnetic interference from other sources.
Moreover, electrical devices in prior art clock generation systems can introduce clock skews into the clock signals as a consequence of
Galloway Paul A.
Wissell Daniel
Compaq Computer Corporation
Hamilton Brook Smith & Reynolds P.C.
Le Dinh T.
LandOfFree
Sinusoidal radio-frequency clock distribution system for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sinusoidal radio-frequency clock distribution system for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sinusoidal radio-frequency clock distribution system for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2569995