Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-08-15
2004-08-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S111000, C438S113000, C438S114000, C438S127000
Reexamination Certificate
active
06773961
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for making leadless semiconductor packages and more specifically to a singulation method used in the leadless packaging process.
2. Description of the Related Art
Lead frame packages have been used for a long period of time in the IC packaging history mainly because of their low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both a faster speed and a smaller size, the traditional lead frame packages have become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array Packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice. The former has been widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages such as CPU and graphic chips. The latter has been widely used in mobile products of which the footprint, package profile and package weight are major concerns.
However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a solution for chip scale and low profile package due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both the footprint and the package profile can be greatly reduced.
FIG. 1
shows a bottom view of a leadless package
10
wherein the leads
11
a
are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package. The die pad
11
b
of the leadless package
10
is exposed from the bottom of the package thereby providing better heat dissipation. Typically, there are four tie bars
11
c
being connected to the die pad
11
b
. The die pad is soldered directly to a matching thermal land on an external PCB providing a low thermal-impedance path to carry heat generated from a semiconductor chip to be mounted on the die pad.
Due to the elimination of the outer leads, leadless packages are featured by lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package
10
very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
The conventional leadless packaging process comprises the following steps.
Firstly, a polyimide (PI) tape was attached to the bottom of a lead frame, and this is to prevent the mold flash problem in the molding process. Typically, a lead frame (denoted as
15
in
FIG. 2
) for used in the aforementioned leadless packages comprises a plurality of units
11
each including a plurality of leads
11
a
arranged at the periphery of a die pad
11
b
, and a plurality of dambars
11
d
between the units
11
. Each die pad
11
b
is connected to the lead frame
15
by four tie bars
11
c.
Then, referring to
FIG. 3
, IC chips
12
are attached to the die pads
11
b
by means of silver epoxy, and the epoxy is cured after die attach. After that, a regular wire-bonding process is performed to make interconnections between the silicon chips
12
and the leads
11
a
of the lead frame
15
. After wire bonding, each of the chips
12
attached on the lead frame
15
is encapsulated in a package body
13
. Typically, an individual molding process was used to accomplish this encapsulation. The PI tape is then removed after the molding process. Finally, post-mold curing and singulation steps were conducted to complete the packaging process. In the singulation process, a resin-bond saw blade is used to cut along the dambars
11
d
thereby obtaining the finished leadless semiconductor packages. Typically, the leadless semiconductor package
10
is mounted onto a substrate, such as a printed circuit board (PC board), by using conventional surface mount technology (SMT).
One major problem during the manufacturing of the package occurred in the singulation process. Typically, the saw blade has to cut through two different materials, i.e., the metal leadframe as well as the molding compound. However, cutting through two different materials not only results in shorter blade life, but also creates lead quality problems such as metal burrs created at the lead cutting ends
14
of the leads
11
a
, which will introduce unsatisfactory coplanarity of the finished packages, thereby complicating and reducing the yield of the later SMT mounting process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a singulation method used in a leadless packaging process which overcomes, or at least reduces the above-mentioned problems of the prior art.
It is another object of the present invention to provide a singulation method used in a leadless packaging process wherein no metal burrs will be created during singulation such that the finished leadless semiconductor packages will have a better coplanarity.
To achieve the above listed and other objects, the present invention provides a singulation method comprising: (a) providing an array of molded products on an upper surface of a lead frame having a plurality of dambars between the molded products, the lower surface of the lead frame being attached with a tape, each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame; and (b) etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.
Since the singulation method is accomplished by etching away the dambars of the lead frame, no mechanical stress will be applied to the finished leadless semiconductor packages. Furthermore, no metal burrs will be created during the etching step; therefore, the finished leadless semiconductor packages will have a good coplanarity thereby enhancing the yield of the SMT mounting process.
According to another embodiment of the present invention, each dambar has a first portion and a second portion connecting the first portion to an adjacent molded product, and, during the etching step, the second portion of each dambar is etched away while the first portion of each dambar substantially remains intact.
The present invention further provides a process for making a plurality of leadless semiconductor packages. The process comprises the steps of: (a) providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement and a plurality of dambars between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad; (b) attaching a plurality of chips onto the die pads of the lead frame; (c) electrically coupling the chips to the leads of the lead frame; (d) attaching a tape onto the lower surface of the lead frame; (e) encapsulating the chips against the upper surface of the lead frame to form a plurality of package bodies each encapsulating one of the chips; (f) etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.
REFERENCES:
patent: 6281047 (2001-08-01), Wu et al.
patent: 6399415 (2002-06-01), Bayan et al.
Kang Kun A
Kim Hyeong No
Lee Jun Hong
Park Hyung Jun
Advanced Semiconductor Engineering INC.
Fourson George
Maldonado Julio J.
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