Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-08-14
2002-12-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S107000
Reexamination Certificate
active
06489218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for making leadless semiconductor packages and more specifically to a singulation method used in the leadless packaging process.
2. Description of the Related Art
Lead frame packages have been used for a long period of time in the IC packaging history mainly because of their low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both a faster speed and a smaller size, the traditional lead frame packages have become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array Packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice. The former has been widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages such as CPU and graphic chips. The latter has been widely used in mobile products of which the footprint, package profile and package weight are major concerns.
However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a solution for chip scale and low profile package due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both the foot print and the package profile can be greatly reduced.
FIG. 1
shows a bottom view of a leadless package
10
wherein the leads
11
a are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package. The die pad
11
b
of the leadless package
10
is exposed from the bottom of the package thereby providing better heat dissipation. Typically, there are four tie bars
11
c
being connected to the die pad
11
b.
Due to the elimination of the outer leads, leadless packages are featured by lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package
10
very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
The conventional leadless packaging process comprises the following steps.
Firstly, a polyimide (PI) tape was attached to the bottom of a lead frame, and this is to prevent the mold flash problem in the molding process. Typically, a lead frame (denoted as
15
in
FIG. 2
) for used in the MAP (mold array package) molding process comprises a plurality of units
11
each including a plurality of leads
11
a
arranged at the periphery of a die pad
11
b
. Each die pad
11
b
is connected to the lead frame
15
by four tie bars
11
c.
Then, referring to
FIG. 3
, IC chips
12
are attached to the die pads
11
b
by means of silver epoxy, and the epoxy is cured after die attach. After that, a regular wire-bonding process is performed to make interconnections between the silicon chips
12
and the leads
11
a
of the lead frame
15
. After wire bonding, the lead frame
15
and the chips
12
attached thereon are encapsulated in a package body
13
. Typically. a MAP molding process was used to accomplish this encapsulation. The PI tape is then removed after the molding process. The molded product is then marked with either laser or traditional ink. Finally, post-mold curing and singulation steps were conducted to complete the packaging process. In the singulation process, a resin-bond saw blade is used to cut the molded product into separate units along predetermined dicing lines to obtain the finished leadless semiconductor packages. Typically, the leadless semiconductor package
10
is mounted onto a substrate, such as a printed circuit board (PC board), by using conventional surface mount technology (SMT).
One major problem during the manufacturing of the package occurred in the singulation process. Since the saw blade has to cut through two different materials, i.e., the metal leadframe as well as the molding compound. Cutting through two different materials not only results in shorter blade life, but also creates lead quality problems such as metal burrs created at the lead cutting ends
14
of the leads
11
a
, which will introduce unsatisfactory coplanarity of the finished packages, thereby complicating and reducing the yield of the later SMT mounting process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a singulation method used in a leadless packaging process wherein the lifetime of the blade used in the singulation operation is significantly increased by avoiding direct cutting of the lead frame.
It is another object of the present invention to provide a singulation method used in a leadless packaging process wherein no metal burrs will be created during singulation such, that the finished leadless semiconductor packages will have a better coplanarity.
In order to achieve the object mentioned above, the present invention provides a singulation method comprising: (a) providing a molded product including a plurality of semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.
Since the cutting streets of the lead frame are etched away during step (b), the lifetime of the blade is significantly increased by avoiding direct cutting of the cutting streets of the lead frame. Furthermore, since no metal burrs will be created when the blade cuts through the molded product, the finished leadless semiconductor packages will have a good coplanarity thereby enhancing the yield of the SMT mounting process.
The present invention further provides a process for making a plurality of leadless semiconductor packages. The process comprises the steps of: (a) providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) attaching a plurality of chips onto the die pad of the lead frame; (c) electrically coupling the chips to the leads of the lead frame; (d) attaching a tape onto the lower surface of the lead frame; (e) encapsulating the chips against the upper surface of the lead frame to form a molded product; (f) removing the tape from the bottom of the molded product; (g) etching the bottom of the molded product with the first metal layer as mask; and (h) cutting the etched molded product along the cutting streets to obtain the leadless semiconductor packages. Preferably, each of the leads is half-etched at its lower surface to form an indentation at a location adjacent to the cutting street. During the step (e), the molding compound will fill in the indentations thereby helping to reduce the “undercut” problem occurred in the isotropic etching pro
Kang Kun-A
Kim Bae Doo
Kim Hyeongno
Lee Junhong
Park Hyung Jun
Advanced Semiconductor Engineering Inc.
Dang Phuc T.
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