Single wire digital interface

Details Single wire digital interface Single wire digital interface

2006-05-30

2006-05-30

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By pulse width or spacing

C327S026000, C327S037000

Reexamination Certificate

active

07053667

ABSTRACT:
A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a known rate for the duration of a received data pulse, and a comparator produces an output that toggles when the filter output exceeds a predetermined threshold. A clock edge is generated when a received pulse terminates; the clock and comparator outputs are provided to a latch circuit. The interface latches a ‘1’ when the received pulse's width is equal to the “first” pulse width, and latches a ‘0’ when the received pulse's width is equal to the “second” pulse width. Data is preferably preceded by a “start-of-packet” (SOP) bit pattern and followed with a “end-of-packet” (EOP) bit pattern.

REFERENCES:
patent: 5210846 (1993-05-01), Lee
patent: 5491440 (1996-02-01), Uehara et al.
patent: 5737140 (1998-04-01), Carr
patent: 5872468 (1999-02-01), Dyke
patent: 6369626 (2002-04-01), Donnelly et al.
Precision CMOS Single Supply Rail-to-Rail Input/Output Wideband Operational Amplifiers, AD8601/AD8602/AD8604, Rev. D, Analog Devices, Inc., Copyright 2003.

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