Single wire bus interface for multidrop applications

Details Single wire bus interface for multidrop applications Single wire bus interface for multidrop applications

1999-04-14

2001-10-02

Myers, Paul R. (Department: 2181)

Multiplex communications

Channel assignment techniques

Polling

C710S100000

Reexamination Certificate

active

06298066

ABSTRACT:

DESCRIPTION
1. Technical Field
The present invention is related to interface circuitry between a master device and a slave device. More specifically, the present invention teaches a variety data communication methods between a master device and multiple analog slave devices using a single line data bus.
2. Background Art
Many electronics applications require a master device to communicate with multiple slave devices for purposes such as data monitoring or process control. A master device may be any device such as a controller, microprocessor or similar device that connects to and communicates with the slave devices. The slave devices may take on a variety of forms depending upon the specific application.
For example, a typical temperature monitoring system utilizes a microprocessor or micro controller as the master device and several temperature sensors as the slave devices. Such a temperature monitoring system is assembled with a dedicated data line coupling each temperature sensor and each microprocessor or micro controller input terminal. This temperature monitoring system allows the microprocessor or micro controller to collect data from each temperature sensing device. The microprocessor or micro controller can then process the collected data. As will be appreciated, this temperature monitoring system requires many data lines and an equal number of input terminals on the microprocessor or micro controller. These data lines form a data bus.
Prior art
FIG. 1
illustrates a multidrop circuit
10
including a microprocessor or micro controller
20
(the master device) coupled to multiple input devices
40
(the slave devices) via a parallel data bus
30
. The microprocessor
20
input terminal I/O
1
is connected to the first input device
1
. The input terminal I/O
2
is connected to the second input device
2
. The input terminal I/O
3
is connected to the third input device
3
. Additional input terminals are connected to additional devices following the similar scheme through to input terminal I/ON and the last input device N, respectively. Each microprocessor or micro controller
20
input terminal is connected to the respective input device
40
by a dedicated data line such as data lines
32
through
38
within the data bus
30
.
The group of dedicated data lines
32
through
38
(and others not shown) taken together make up the data bus
30
. In this prior art example, the bus is said to be a parallel bus since each device is assigned a discrete data line that runs together, or parallel, to one another between each individual input device and the microprocessor or micro controller input terminal.
When input device
1
produces a signal, the signal is transmitted through a dedicated data line in the data bus
30
to the micro controller
20
input terminal I/O
1
. Data output from each input device
40
is input to the microprocessor or micro controller
20
on a dedicated microprocessor or micro controller
20
input terminal.
A parallel data bus
30
requirement increases the number of I/O terminals required on the microprocessor or micro controller
20
. If, for example, the multidrop system
10
of
FIG. 1
had seventy-five input devices, a corresponding seventy-five input terminals on the microprocessor or micro controller
20
would also be required. This requirement increases the complexity and cost of the microprocessor or micro controller
20
. In addition, the parallel data bus
30
adds additional complexity and cost to the data monitoring or communication system. These complex requirements increase the overall cost of production and material for data monitoring and communication systems.
As will be appreciated, a common application has the slave or input devices
40
as analog voltage output devices such as a temperature, voltage, pressure or acceleration sensor or any other analog output device. Analog input devices typically produce a variable voltage signal where the master device is capable of processing the voltage using a internal or external analog to digital converter (ADC) thereby converting the analog signal to digital data. The microprocessor or micro controller can then process the digital data.
Analog input devices may also produce a digital like signal if they produce discrete bits. Discrete bit devices produce only two types of signals, a high logic state and a low logic state. In many systems a low logic state corresponds to a high voltage state, typically V
cc
. In such systems, the high logic state corresponds to a low voltage state, typically <1 vdc. The microprocessor or micro controller may process this data bit as a single data bit or as an analog signal as described above.
Prior art
FIG. 2
illustrates another multidrop circuit
100
having a microprocessor
20
coupled to a access system
110
by multiple data lines of the parallel data bus
105
. The access system is coupled to multiple input devices
120
by a single data line of the serial data bus
130
. In this prior art example, the system has two data buses. The first data bus is a parallel data bus
105
coupling the microprocessor
20
with the access system
110
. The second data bus is a serial data bus
130
coupling the access system
110
with the multiple input devices
120
. The serial data bus
130
transports data from multiple input devices or components.
In this example, the serial data bus
130
transports data from the access system
110
and the multiple input devices
120
. When the access system
110
needs an input from input device
1
, the access system
110
will send a request or polling signal on the serial data bus
130
to input device
1
. Input device
1
has been assigned a unique polling signal to respond to. Polling signals may be analog voltage or digital data stream instruction. Input device
1
only produces a signal after requested or polled by the access system
110
. Similarly, subsequent input devices
2
,
3
, . . . N will be assigned unique polling signals and polled for data.
This prior art example reduces the number of and the dedicated data lines required in the parallel data bus
105
and the number of I/O terminals on the microprocessor
20
but adds the cost and complexity of the additional components such as the access system
110
, the input devices
120
capable of responding to polling signals, and the second data bus
130
. This adds additional components, complexity and cost to the system.
What is needed is a protocol for a multidrop circuit that lacks the complexity of both a parallel data bus and a serial data bus or the addition of access system type interface devices, yet is still capable of accurate data communication data across the multidrop circuit.
DISCLOSURE OF THE INVENTION
In order to achieve the foregoing the teaching of the present invention enables data communications between multiple devices over a single wire bus. This single-wire interface can be used for sensors, amplifiers, analog-to-digital converters (ADCs), or any other circuit which would normally have an electrical output. Advantages of the present invention include a reduction in device pin count, conservation of the limited number of I/O pins on the control device, and reduced board layout complexity.
Speaking generally, each slave device coupled to the single wire bus interface is assigned a different response time window. For example, each slave device may be manufactured with a different time conversion function assigned to encode its analog data. This enables multiple parts to respond to an initial trigger signal generated by the master device without overlapping responses being generated on the single wire bus interface.
A first aspect of the present invention teaches a method for controlling communication over the single wire bus interface for a multidrop circuit. Generally, the multidrop circuit includes a master device and a first slave device coupled together via the single wire bus and the first slave device is assigned a first response window. Steps involved in this method include initiating a timing sequence by transmitting a sta

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