Single twist layout and method for paired line conductors of int

Details Single twist layout and method for paired line conductors of int Single twist layout and method for paired line conductors of int

1995-12-04

1996-07-09

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257664, 257907, 365 63, H01L 2710

Patent

active

055347320

ABSTRACT:
An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

REFERENCES:
patent: 4914502 (1990-04-01), Lebowitz et al.
patent: 5097441 (1992-03-01), Cho et al.
Yoshihara et al., "A Twisted Bit Line Technique for Multi-Mb DRAMs," IEEE International Solid-State Circuits Conference, pp. 238-239, Feb. 1988.
Oowaki et al., "A 33 ns 64 Mb DRAM," IEEE International Solid-State Circuits Conference, pp. 114-115, Feb. 1991.

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