Single tub transistor means and method

Details Single tub transistor means and method Single tub transistor means and method

1987-07-01

1988-09-20

Roy, Upendra

Fishing, trapping, and vermin destroying

357 34, 357 91, 437 29, 437 31, 437 26, 437 69, H01L 21225, H01L 2120

Patent

active

047725664

ABSTRACT:
A means and method for forming a single tub transistor, such as for example a vertical NPN bipolar transistor surrounded by an isolation wall, is described. Multiple polysilicon and dielectric layers are employed in conjunction with a master mask and with isotropic and anisotropic etching procedures to define the contacts and active regions of the device without resorting to precision alignments. Sub-micron lateral device contacts are easily achieved even with comparatively coarse lithographic methods through use of sidewall spacers for controlled narrowing of critical device openings. The finished device is especially compact, has low resistance contacts for its size, and provides very high speed operation.

REFERENCES:
patent: 4430793 (1984-02-01), Hart
patent: 4495010 (1985-01-01), Kranzer
patent: 4545114 (1985-10-01), Ito et al.
patent: 4581319 (1986-04-01), Wieder et al.
patent: 4640721 (1987-02-01), Uehara et al.
patent: 4641416 (1987-02-01), Iranmanesh
patent: 4641419 (1987-02-01), Kudo
patent: 4689872 (1987-09-01), Appels et al.

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