Single transistor per cell EEPROM memory device with bit line se

Details Single transistor per cell EEPROM memory device with bit line se Single transistor per cell EEPROM memory device with bit line se

1993-11-08

1994-10-11

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 36523003, G11C 800, G11C 700

Patent

active

053553470

ABSTRACT:
An EEPROM memory array divided into a plurality of sectors having R word lines with each sector containing S bit lines, for a total of R.times.S bit-line/word-line intersections. At each intersection there is a single transistor EEPROM memory cell with its drain connected to a bit line and its gate connected to a word line. The sources of all the cells in each sector are interconnected to a sector select line. The Fowler-Nordheim tunneling mechanism is used to accomplish erase and write operations to the memory cells. The embodiment also includes a data latch array having R data latch rows, each of which is dedicated to storing a group of S data bits to be serially written into cells of the memory via a particular one of the R word lines. A data input-output buffer has S data inputs for supplying groups of S data bits in sequential steps to S latches within each of the data latch rows, to form S columns of R data bits within the data latch array. The EEPROM memory has sector and bit line select circuitry to activate a particular sector, de-activate the others, and select a particular bit line within a sector. During the write operation the bit line and sector select circuitry work together with high voltage pump circuitry, memory control logic, timing circuitry, and address circuitry to cause each column of R data bits in the data latch array to be passed via the R word lines and written into the R cells connected to a selected bit line. This writing of R cells via the word lines is done in a single step to the cells connected to the particular bit line; the next column of latched data being written into the memory cells corresponding to another bit line until the entire sector is written.

REFERENCES:
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patent: 5204841 (1993-04-01), Chappell et al.
patent: 5247485 (1993-09-01), Ide
patent: 5323355 (1994-06-01), Kato
Masuoka, Fujio et al.; "A 256-kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 4 (Aug. 1987).
Cioaca, Dumitru et al.; "A Million-Cycle CMOS 256K EEPROM", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5 (Oct. 1987).
Nakayama, Takeshi et al.; "A 5-V-Only One-Stransistor 256K EEPROM with Page-Mode Erase", IEEE Journal of Solid-State Circuits, vol. 24, No. 4 (Aug. 1989).
McConnell, Mike et al.; "An Experimental 4-Mb Flash EEPROM with Sector Erase", IEEE Journal of Solid-State Circuits, vol. 26, No. 4 (Apr. 1991).
Momodomi, Masaki et al.; "A 4-Mb NAND EEPROM with Tight Programmed V.sub.t Distribution", IEEE Journal of Solid-State Circuits, vol. 26, No. 4 (Apr. 1991).

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