Single transistor non-volatile electrically alterable semiconduc

Details Single transistor non-volatile electrically alterable semiconduc Single transistor non-volatile electrically alterable semiconduc

1991-08-21

1993-04-13

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365149, 257288, G11C 1140

Patent

active

052028500

ABSTRACT:
A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer. The first section extends over a portion of the channel region and over the source region. A second section is disposed over the top wall portion of the second insulating layer to minimize capacitive coupling with the floating gate.

REFERENCES:
patent: 3825946 (1974-07-01), Frohman-Bentchkowsky
patent: 4729115 (1988-03-01), Kauffmann et al.

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