Static information storage and retrieval – Floating gate – Particular biasing
Patent
1990-01-22
1991-07-02
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
365186, G11C 1140
Patent
active
050291300
ABSTRACT:
A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the drain region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate. Programming is accomplished by electrons from the source migrating through the channel region underneath the control gate and then by abrupt potential drop injecting through the first insulating layer into the floating gate.
REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentcnkowsky
patent: 4274012 (1981-06-01), Simko
patent: 4366555 (1982-12-01), Hu
patent: 4599706 (1986-07-01), Guterman
patent: 4698787 (1987-10-01), Mukherjee et al.
"Electron Tunneling in Non-Planar Floating Gate Memory Structure", by R. K. Ellis et al., 1982, IEEE.
"A New NMOS Charge Storage Effect", by H. G. Dill et al., Solid State Electronics, 1969, vol. 12, pp. 981-987.
Fears Terrell W.
Silicon Storage Technology, Inc.
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