Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-03-28
2003-08-05
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S287000
Reexamination Certificate
active
06602720
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor technology and more particularly to metal-ferroelectric-insulator semiconductor (MFIS) transistor structures, and methods of fabrication. An MFIS transistor is similar to an MFOS transistor, but is not limited to structures that use oxide as the insulator material.
Previously, single transistor ferroelectric memory transistors have utilized a ferroelectric electrode stack, comprising a ferroelectric gate with a top electrode. The device would be formed by depositing a ferroelectric material, followed by an overlying metal layer. The layers would then be plasma etched. Plasma etching degrades the ferroelectric properties of the ferroelectric gate, thereby reducing the reliability of the memory transistor. The ferroelectric material also needed to be passivated to prevent contamination from hydrogen. Passivation was also used to reduce unwanted interactions between the ferroelectric material and underlying oxide.
SUMMARY OF THE INVENTION
A ferroelectric transistor structure is provided comprising a ferroelectric gate overlying a semiconductor substrate. The ferroelectric gate has a bottom and sides surrounded by high-k material, and a top covered with a top electrode. The top electrode and the high-k material serve to encapsulate the ferroelectric gate, thereby reducing, or eliminating, contamination due to oxygen, hydrogen or other contaminants. The high-k material along the bottom of the ferroelectric gate also serves as a gate dielectric.
A method of forming the ferroelectric gate structure of the present invention is also provided. A sacrificial gate structure is formed overlying a substrate and removed to produce an open gate region. A high-k insulator is deposited over the substrate, including the open gate region. A ferroelectric material is deposited over the high-k insulator and then polished using CMP. A top electrode is then formed over the remaining ferroelectric material. The combination of the top electrode and the high-k insulator serve to encapsulate and protected the ferroelectric material.
The high-k insulator is preferably ZrO
2
, zirconium silicate, Zr—Al—Si—O, HfO
2
, hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide Ta
2
O
5
, or other suitable material
The ferroelectric material is preferably PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, YMnO
3,
or other suitable material.
The top electrode is preferably iridium, platinum, ruthenium, iridium oxide, platinum oxide, ruthenium oxide, or other suitable material.
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Hsu Sheng Teng
Zhang Fengyan
Foong Suk-San
Fourson George
Krieger Scott C.
Rabdau Matthew D.
Ripma David C.
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