Single transistor electrically programmable memory device and me

Details Single transistor electrically programmable memory device and me Single transistor electrically programmable memory device and me

1986-08-14

1989-09-19

James, Andrew J.

357 234, 357 2315, 357 54, H01L 2978

Patent

active

048686190

ABSTRACT:
An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.

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patent: 3500142 (1970-03-01), Kahng
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patent: 4291321 (1981-09-01), Pfleiderer
patent: 4295150 (1981-10-01), Adam
patent: 4471405 (1984-09-01), Howard et al.
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4630086 (1986-12-01), Sato et al.
Insulating Films on Semiconductors, Kuiper et al., pp. 118-120, 1983.

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