Single transistor EEPROM memory cell

Details Single transistor EEPROM memory cell Single transistor EEPROM memory cell

1990-12-11

1993-06-22

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365186, 365218, 365900, G11C 1300

Patent

active

052220400

ABSTRACT:
A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a tunneling of charge can take place between the drain and the floating gate by means of a system of applied voltages to the control gate and drain.

REFERENCES:
patent: 4366555 (1982-12-01), Birdsall
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4758986 (1988-07-01), Kuo
patent: 4884239 (1989-11-01), Ono et al.
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 4996571 (1991-02-01), Kume et al.
Gill, M., et al., "A 5-Volt Contactless Array . . . " IEEE IEDM 88, 1988, pp. 428-430.

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