Single transistor cell for electrically-erasable programmable re

Details Single transistor cell for electrically-erasable programmable re Single transistor cell for electrically-erasable programmable re

1986-12-29

1988-08-23

Clawson, Jr., Joseph E.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 54, 365185, H01L 2978

Patent

active

047664738

ABSTRACT:
A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

REFERENCES:
patent: 4317272 (1982-03-01), Kuo et al.
patent: 4668970 (1987-05-01), Yatsuda et al.
patent: 4691216 (1987-09-01), Terada et al.
"How Seeq is Pushing EEPROMS to 1-Mb Densities", Electronics, Aug. 21, 1986, pp. 53-56.

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