Single transistor cell for electrically-erasable programmable re

Details Single transistor cell for electrically-erasable programmable re Single transistor cell for electrically-erasable programmable re

1987-02-20

1988-07-19

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365189, 365218, 357 45, G11C 1300, G11C 1140

Patent

active

047589868

ABSTRACT:
A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

REFERENCES:
patent: 4531203 (1985-07-01), Masyoka et al.

Affiliated with

Also associated with

Rating

Single transistor cell for electrically-erasable programmable re does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single transistor cell for electrically-erasable programmable re, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single transistor cell for electrically-erasable programmable re will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-601497