Single-temperature-trimmable FET input circuit having active cha

Details Single-temperature-trimmable FET input circuit having active cha Single-temperature-trimmable FET input circuit having active cha

1989-09-18

1992-06-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072021, 3073032, 307572, 357 41, 357 51, H03K 17687, H01H 3776

Patent

active

051245965

ABSTRACT:
In an FET differential input, preferably using a quad set of devices according to the teaching of U.S. Pat. No. 3,729,660, the channel of each transistor is formed in a piecewise manner, of multiple segments. Each channel segment is associated with a corresponding drain segment (i.e., these are multi-drain devices). Each drain segment is connected in series with a thin-film resistor. The channel area associated with each drain segment can be selectively removed from the circuit by cutting the connected resistor with a laser. The device's channel area (and its effective width to length ratio, Z/L) is thereby alterable. The thin film resistors are cut as the offset is measured, until an acceptably low (effectively zero) offset is obtained. This trimming operation can be performed at room temperature, and yields not only a near zero offset voltage, but also near zero drift. CMRR, further, will be maximized. Neither operating current ratio nor drain voltage need be, or is, changed.

REFERENCES:
patent: 3729660 (1973-04-01), Maidique
patent: 4210875 (1980-07-01), Beasom
patent: 4306246 (1981-12-01), Davies et al.
patent: 4885481 (1989-12-01), Hobbs et al.
patent: 4922134 (1990-05-01), Hoffmann et al.

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