Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-27
2004-06-22
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S230080
Reexamination Certificate
active
06754107
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a single supply voltage, nonvolatile memory device with cascoded column selection and simultaneous word read/write operations.
In particular, the present invention advantageously, but not exclusively, finds application in nonvolatile phase change memory devices, to which the following discussion will make explicit reference without any loss of generality thereby.
BACKGROUND OF THE INVENTION
As is known, nonvolatile memory devices comprise a memory array formed by memory cells arranged in rows and columns, wherein word lines connect the gate terminals of the cells arranged on a same row and bit lines connect the array access device terminals (commonly drain terminals) of the cells arranged on one and the same column.
Individual rows of the memory array are addressed by a row decoder which receives an encoded address and biases the word line of the row being addressed at a stable and precise voltage, the value whereof depends upon the operation to be performed (read, program, verify, erase), while individual columns of the memory array are selected by a column selector which receives the outputs of a column decoder supplied with the above encoded address. The bitline of the column being addressed is biased such as to ensure that the array access device terminal of the memory cell addressed is biased at a preset electrical potential, which depends on the operation to be performed; this potential must be precise, stable and controlled since its precision affects not only the precision of the levels programmed in the memory cells, but also the programming time of the memory cells or, in read operation, the correct detection of the cell's content.
Phase change memory (PCM) devices are based on storage elements that use a class of materials which have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous, disorderly phase to a crystalline or polycrystalline, orderly phase, and the two phases are associated to considerably different values of resistivity.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase-change cells. The chalcogenide that currently offers the most promise is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5) and is widely used for storing data in overwritable disks.
In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa. The characteristics of the chalcogenides in the two phases are shown in FIG.
1
. As may be noted, at a given read voltage, here designated by Vr, there is a variation in resistance of more than 10.
Phase change may be obtained by locally increasing the temperature, as shown in FIG.
2
. Below 150° C. both phases are stable. Above 200° C. (nucleation starting temperature, designated by Tx), there takes place fast nucleation of the crystallites, and, if the material is kept at the crystallization temperature for a sufficient length of time (time t2), it changes its phase and becomes crystalline. To bring the chalcogenide back into the amorphous state, it is necessary to raise the temperature above the melting temperature Tm (approximately 600° C.) and then to cool the chalcogenide off rapidly (time t1).
From the electrical standpoint, it is possible to reach both the critical temperatures, namely the crystallization temperature and the melting point, by causing a current to flow through a resistive element which heats the chalcogenic material by the Joule effect.
The basic structure of a phase change storage element
1
which operates according to the principles described above is shown in FIG.
3
and comprises a resistive element
2
(heater) and a programmable element
3
. The programmable element
3
is made with a chalcogenide and is normally in the crystalline state in order to enable a good flow of current. One part of the programmable element
3
is in direct contact with the resistive element
2
and forms a phase change portion
4
.
If an electric current having an appropriate value is made to pass through the resistive element
2
, it is possible to heat the phase change portion
4
selectively up to the crystallization temperature or to the melting temperature and to cause phase change.
The state of the chalcogenic material can be measured by applying a sufficiently small voltage, such as not to cause a sensible heating, and by then reading the current that is flowing. Given that the current is proportional to the conductivity of the chalcogenide, it is possible to discriminate wherein state the chalcogenide is.
Of course, the chalcogenide can be electrically switched between different intermediate states, thus affording the possibility of obtaining a multilevel memory.
In practice, a phase change memory element or PCM storage element
1
can be considered as a resistor which conducts a different current according to its phase. In particular, the following convention is adopted: a phase change storage element is defined as “set” when, once it is appropriately biased, it conducts a detectable current (this condition may be associated to a logic condition “1”) and as “reset” when, in the same biasing conditions, it does not conduct current or conducts a much lower current than that of a cell that is set (logic condition “0”).
The use of PCM storage elements has already been proposed in memory arrays formed by a plurality of memory cells arranged on rows and columns. In order to prevent the memory cells from being affected by noise caused by adjacent memory cells, generally each memory cell comprises a PCM storage element of the type described above and a selection element, such as a MOS transistor or a diode, in series to the PCM storage element.
When the selection element is a diode, each cell is connected at the intersection of two selection lines, perpendicular to one another, one of which is parallel to the rows of the memory array, while the other is parallel to the columns.
When the selection element is a transistor, different solutions are known which are essentially based upon biasing the source terminal of the selection element at variable voltages that depend upon the reading or programming operation (set, reset) of the memory. For example, according to U.S. Pat. No. 6,314,014, a first terminal of the PCM storage element is biased at a biasing voltage the value of which depends upon the operation (either reading or programming) of the memory cell, a second terminal of the PCM storage element is connected to a drain terminal of the selection transistor, the gate terminal of the selection transistor is connected to a row line, and the source terminal of the selection transistor is connected to a column line. In practice, selection of the memory cell takes place via the source and gate terminals of the selection transistor. Alternatively, the drain terminal of the selection transistor can be biased at the biasing voltage, and the memory cell can be coupled between the source terminal and its own column line.
It is moreover known that nonvolatile memory devices are typically of a single supply voltage type; namely, they receive from outside a single supply voltage currently having a value of 3 V±10% or else 1.8 V±10%; hence voltages having much higher values than the supply voltages and required in the various operations performed on the memory cells (read, program, verify, erase) are generated inside the nonvolatile memory device by voltage boosting circuits, generally known as “voltage boosters” or “charge pumps”.
The boosted voltages supplied by voltage boosting circuits are, however, generally far from stable, and consequently are regulated and stabilized by voltage regulators.
FIG. 4
is a schematic illustration of a known nonvolatile memory device, of which only the parts necessary for understanding the pr
Bedeschi Ferdinando
Khouri Osama
Carlson David V.
Jorgenson Lisa K.
Phung Anh
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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