Coating apparatus – Gas or vapor deposition
Reexamination Certificate
2000-04-13
2002-06-11
Bueker, Richard (Department: 1763)
Coating apparatus
Gas or vapor deposition
C156S345420
Reexamination Certificate
active
06402848
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-117245, filed Apr. 23, 1999; and No. 11-207327, filed Jul. 22, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a single-substrate-treating apparatus for a semiconductor processing system, which performs processing such as film formation or annealing of target substrates such as semiconductor wafers one by one. Semiconductor processing means herein various processes executed to manufacture a semiconductor device on a target substrate such as a semiconductor wafer or LCD substrate by forming a predetermined pattern of a semiconductor layer, insulating layer, and conductive layer on the target substrate, or a structure including interconnections and electrodes connected to the semiconductor device.
In manufacturing a semiconductor integrated circuit, a target substrate such as a semiconductor wafer is repeatedly subjected to various processes including film formation, etching, oxidation/diffusion, and annealing/modification. In these processes, a process gas necessary in correspondence with the type of process is introduced into a process chamber. For example, a film formation gas is supplied for film formation, and ozone gas is supplied for annealing/modifying.
The process chamber is evacuated to maintain predetermined pressure preferable to the type of process. A gas flow generated upon evacuation is required to be uniform with respect to the surface of the semiconductor wafer for the purpose of maintaining high planar uniformity of the process.
A conventional general single-substrate-treating apparatus for a semiconductor processing system will be described.
FIG. 6
is a schematic view showing a conventional general annealing/modifying apparatus.
FIG. 7
is a sectional view taken along a line VII—VII in FIG.
6
.
As shown in
FIG. 6
, this annealing/modifying apparatus has a closed process chamber
2
made of aluminum and having, e.g., a rectangular section. In the process chamber
2
, a work table
6
stands upright on the bottom portion of the process chamber through a strut
4
. The work table
6
incorporates a heater
8
to heat a target substrate or a semiconductor wafer W placed on the surface of the work table
6
. A ring-shaped shower head
10
formed from quartz is disposed above the work table
6
to introduce a process gas, e.g., ozone into the process chamber
2
. The process chamber
2
has a transparent window
12
at its ceiling. The wafer surface is irradiated with ultraviolet rays UV emitted from an external UV lamp
14
.
On a bottom portion
16
of the process chamber
2
, four exhaust ports
18
(
FIG. 7
) are formed at positions obliquely under the work table
6
. An exhaust tube
20
is connected to each exhaust port
18
. The exhaust tubes
20
join each other on the downstream side and are connected to a vacuum pump (not shown) for evacuating the process chamber
2
.
In this annealing/modifying apparatus, the wafer W on the work table
6
is heated and simultaneously affected by ozone gas excited by the ultraviolet rays UV. With this process, for example, a Ta
Ox
(tantalum oxide) film formed on the surface of the wafer W is annealed and modified.
In this apparatus, the planar uniformity of processing may not be maintained sufficiently high. This problem is becoming conspicuous as the semiconductor wafer size increases from 6 or 8 inches to 12 inches. Additionally, in the above apparatus, the target substrate or a thin film thereof may be contaminated by particles of a metal or by-product.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a single-substrate-treating apparatus for a semiconductor processing system, which can maintain high planar uniformity of processing.
It is another object of the present invention to provide a single-substrate-treating apparatus for a semiconductor processing system, which rarely contaminates a target substrate with particles of a metal or by-product.
According to the present invention, there is provided a single-substrate-treating apparatus for a semiconductor processing system, comprising:
a hermetic process chamber;
a work table disposed in the process chamber and having an upper surface on which a target substrate is placed;
a supply mechanism for supplying a process gas into the process chamber from a position opposing the upper surface of the work table;
an exhaust chamber connected to a bottom portion of the process chamber through a first opening below the work table, the first opening having a planar contour smaller than that of the work table, and the planar contours of the work table and the first opening being arranged substantially concentrically with each other; and
an exhaust mechanism for exhausting the process chamber through the exhaust chamber and the first opening.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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patent: 5871586 (1999-02-01), Crawley
patent: 6063199 (2000-05-01), Sajoto
patent: 6280793 (2001-08-01), Atwell
patent: 6300600 (2001-10-01), Ratliff
patent: 62-199019 (1987-09-01), None
patent: 63-56914 (1988-03-01), None
patent: 1-251710 (1989-10-01), None
patent: 9-167762 (1997-06-01), None
Horiguchi Takahiro
Okase Wataru
Takanabe Eiichiro
Bueker Richard
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tokyo Electron Limited
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