Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
1999-11-30
2003-01-28
Leja, Ronald W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06512662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to protection for semiconductor integrated circuits from over-voltage and over-current conditions caused by electrostatic discharge (ESD). The present invention relates more specifically to a single structure ESD protection circuit using active devices integrated therein.
2. Description of Prior Art
ESD events, which are inevitable in integrated circuit (IC) manufacturing, assembly, and application, generate huge over-current and over-voltage pulses that can fatally damage electronic components. ESD failure emerges as the major reliability concern to the IC industry, accounting for up to thirty percent of field failures. Therefore, industrial standards generally require on-chip ESD protection circuits for all IC chips.
In general principle, an ESD protection circuit is off, or open in normal operation and is triggered on, or closed, during an ESD event to form a low impedance path to shunt the current surge and to clamp the pin voltage to a sufficient level, thereby protecting an IC part from being damaged. To form a complete ESD protection scheme, shown in
FIG. 1
, protection against ESD pulses of two opposite polarities, or pulse modes, i.e., positive and negative, along a path from each input/output (I/O) pin to both power supply, or V
DD
, and ground, or GND, as well as the path between V
DD
to GND are required to achieve all direction protection.
Various on-chip ESD protection designs are known. Traditional solutions generally offer low impedance discharging paths in one direction only while relying on a passive current path with much higher impedance for protection in the opposite direction. This means four circuits may be needed for each I/O pin and an additional circuit between supply and ground, if a high level of ESD protection is desired. This solution consumes significant chip area, e.g., up to thirty percent of the whole chip.
Other proposed solutions, such as U.S. Pat. No. 5,739,998 to Wada, may use various combinations of parasitic diodes and SCRs with transistor areas to provide protection for the various paths and pulse modes. Parasitic resistance and capacitance may negatively affect IC performance, as well as offer reduced protection performance because of higher impedance and slower reaction times which may not be adequate for very high speed chips such as RF IC's. In short, there is great need for a single structure circuit covering all ESD paths and pulse modes utilizing only active devices while utilizing minimal chip area.
In
Proceedings of IEEE
7
th International Symposium on the Physical and Failure Analysis of IC
's, pp. 151-155, 1999, an ESD protection scheme is disclosed offering improved performance in a compact area providing low impedance active discharge paths in both directions to shunt ESD pulses in two opposite polarities. It therefore requires only two circuits for each I/O pin and a separate ESD circuit for V
DD
to GND for full ESD protection as seen in FIG.
2
. This scheme represents a further size reduction in silicon area consumption over previously known schemes.
SUMMARY OF THE INVENTION
An ESD protection structure according to the present invention forms a single circuit which has a N-well, or N-substrate, having three separate P diffusions (hereinafter “tubs”) with the first and third P-tubs having N+ and P+ diffusions for ohmic contact therein. A second P-tub interposed between the first and third tub has two N+ diffusions and one P+ diffusion therein. The I/O pin, or anode, is connected across each of the two N+ diffusions and the P+ diffusion of the second P-tub. The V
DD
, or supply, pin, cathode one, is connected across the N+ and P+ diffusions of the third tub. The ground pin, cathode two, is connected across the P+ and N+ diffusions of the first P-tub. The structure thereby forms six bipolar transistors and eight parasitic resistors and thereby forming a circuit of five thyristors for control of the ESD over-current/over-voltage conditions. The structure set forth herein preferably forms symmetrical upper and lower protection subcircuits. The upper and lower subcircuit have one PNP transistor and two NPN transistors and four resistors creating two thyristors in each protection subcircuit, or structure half, and one thyristor formed between the subcircuits. One protection subcircuit provides positive and negative pulse protection between the I/O pin and the V
DD
pin. The other protection subcircuit provides positive and negative pulse protection between the I/O pin and the ground pin. The shared thyristor provides both positive and negative pulse protection between the ground pin and the V
DD
pin. By being built on a single substrate and providing protection against both polarities of surge along all paths, the present invention provides maximum protection with minimal use of IC surface area. The present structure operates symmetrically and responds in the sub-nanosecond range, providing low holding voltage, low discharge impedance adjustable trigger voltage and high failure threshold voltages.
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Illinois Institute of Technology
Leja Ronald W.
Pauley Petersen Kinne & Erickson
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