Coded data generation or conversion – Digital code to digital code converters – To or from bit count codes
Reexamination Certificate
2007-03-13
2007-03-13
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from bit count codes
C341S050000, C326S082000
Reexamination Certificate
active
11314236
ABSTRACT:
An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
REFERENCES:
patent: 5228037 (1993-07-01), Yonehara
patent: 5337252 (1994-08-01), Lac et al.
patent: 5689258 (1997-11-01), Nakamura et al.
patent: 5763908 (1998-06-01), Han et al.
patent: 6708314 (2004-03-01), Trivedi et al.
patent: 6880026 (2005-04-01), Imming et al.
patent: 2003/0025122 (2003-02-01), Nakamura et al.
Lin Li et al., A Crosstalk Aware Interconnect with Variable Cycle Transmission, Feb. 16, 2004, IEEE, Proceedings of the Design, Automation and Test in Europe Conference & Exhibition (DATE'04) vol. 1, pp. 102-107.
Rejesh Kumar et al.; “Interconnect and Noise Immunity Design for the Pentium 4 Processor,” Intel Technology Journal Q1, 2001; pp. 1-2, 2003. no month.
Daniel Wiklund et al., “SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems;” Eight Unnumbered Pages, 2003, no month.
Ismail et al., “Repeater Insertion inRLCLines for Minimum Propagation Delay”, Jul. 1999 IEEE, pp. Vl-404-Vl-407.
Maged Ghoneima et al., “Utilizing the Effect of Relative Delay on Energy Dissipation in Low-Power On-Chip Buses;” pp. 1-25, vol. 12, No. 12 Dec. 2004.
Muhammad Khellah et al., “Static Pulsed Bus for On-Chip Interconnects,” 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 78-79, 2002, no month.
Youngsoo Shin et al, “Coupling-Driven Bus Design for Low-Power Application-Specific Systems” DAC2001, Jun. 18-22, 2001, Las Vegas, Nevada.
Mircea R. Stan, et al, “Bus-Invert Coding for Low-Power I/O,” IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 3, No. 1, Mar. 1995.
Kei Hirose et al., “A Bus Delay Reduction Technique Considering Crosstalk,” 5 unnumbered pages, pp. 441-445, 2000.
Caputa Peter
De Vivek K.
Ghoneima Maged M.
Ismail Yehea I.
Khellah Muhammad M.
Fleshner & Kim LLP
Jeanglaude Jean Bruner
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