Single-stack implementation of a Reed-Solomon encoder/decoder

Details Single-stack implementation of a Reed-Solomon encoder/decoder Single-stack implementation of a Reed-Solomon encoder/decoder

1992-07-09

1995-03-07

Baker, Stephen M.

Excavating

3647461, 364754, 364761, H03M 1300, G06F 772

Patent

active

053965027

ABSTRACT:
The present invention is for a Error Correction Unit (ECU) that uses a single stack architecture for the generation, reduction and evaluation of the polynomials involved in the correction of a Reed-Solomon code. The circuit uses the same hardware to generate the syndromes, reduce the .OMEGA.(x) and .LAMBDA.(x) polynomials and evaluate the .OMEGA.(x) and .LAMBDA.(x) polynomials. Some of the specifics involved in calculating and reducing the polynomials mentioned above are novel as well. First, the implementation of the general Galois field multiplier is new and faster than previous implementations. Second, the circuit for implementing the Galois field inverse function has not appeared in prior art designs. Third, a novel method of generating the .OMEGA.(x) and .LAMBDA.(x) polynomials (including alignment of these polynomials prior to evaluation) is utilized. Fourth, corrections are performed in the same order as they are received using a premultiplication step prior to evaluation. Fifth, a novel method of implementing flags for uncorrectable errors is used. Sixth, the ECU is data driven in that nothing happens if no data is present. Finally, interleaved data is handled internally to the chip.

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Laws, B. A. Jr. et al., "A Cellular-Array Multiplier for GF (2.sup.m)", IEEE Transactions on Computers, Dec. 1971, pp. 1573-1578.
Wang, C. C. et al., "VLSI Architectures for Computing Multiplications and Inverses in GF (2.sup.m)", IEEE Transactions on Computers, vol. C-34, No. 8, Aug. 1985, pp. 709-717.
Cavanagh, J. J. F., Digital Computer Arithmetic, McGraw-Hill Book Company, 1984, pp. 188, 192, 193.

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