Patent
1994-03-08
1996-08-27
Ellis, Richard L.
G06F 1576
Patent
active
055510124
ABSTRACT:
An upgradeable/downgradeable computer system is made capable of being driven by more than one model of central processing units, including at least one socket means capable of being plugged with different model of central processing units, an identifying circuit capable of identifying the model of the central processing unit in the socket means and generating an identifying signal, a clock generator responsive to the identifying signal for generating a clock signal acceptable to the model of the central processing unit in the socket means, and a means responsive to the identifying signal for gating and inhibiting a plurality of input/output signals of the central processing unit in the socket means.
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Chuang Te-Chih
Lee Yi-Hsien
Liao Yunn-Hung
Wei Lung
Acer Incorporated
Ellis Richard L.
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