Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-07-19
2004-08-03
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010
Reexamination Certificate
active
06771084
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to burn-in and test of microelectronic devices, specifically to contact assemblies used for connecting electrical signals to integrated circuits during burn-in and test of individual chips and of full wafers.
Microelectronic devices are subjected to a series of test procedures during the manufacturing process in order to verify functionality and reliability. The testing procedures conventionally include wafer probe testing, in which microelectronic device chips are tested to determine operation of each chip before it is diced from the wafer and packaged. Probe cards built of long cantilever wires are used to test one or several chips at a time while on the wafer.
Typically, not all chips on a wafer are found to be operable in the wafer probe test, resulting in a yield of less than 100% good devices. The wafer is diced into individual chips, and the good chips are then assembled into packages. The packaged devices are dynamically burned-in by loading them into sockets on burn-in boards and electrically operating them at a temperature of from 125° C. to 150° C. for a burn-in period of 8 to 72 hours in order to induce any defective devices to fail. Burn-in accelerates failure mechanisms that cause infant mortality or early failure of the devices, and allows these defective devices to be weeded out by a functional electrical test before they are used commercially.
A full functional test is done on packaged devices, which are operated at various speeds in order to categorize each by maximum speed of operation. Testing discrete packaged devices also permits elimination of any devices that failed during the burn-in process. Burn-in and test of packaged devices is accomplished by means of sockets specially suited to the burn-in conditions and to high speed testing respectively. Conventional manufacturing processes are expensive and time consuming because of a repeated handling and testing of individual discrete devices through a lengthy set of steps that adds weeks to the total manufacturing time for the device.
A considerable advantage in cost and in process time can be obtained by burn-in and test of the wafer before it is diced into discrete devices. Additional savings can be obtained by fabricating chip size packages on each device on a wafer before the wafer is diced into discrete devices. A considerable effort has been expended by the semiconductor industry to develop effective methods for wafer level burn-in and test in order to gain benefits of a greatly simplified and shortened process for manufacturing microelectronic devices. In order to reap these benefits, it is necessary to provide means to burn-in and speed test chips before they are diced from the wafer into individual discrete devices.
Conventional cantilever wire probes are not suited to burn-in and speed test of devices on the wafer. Cantilever wire probes are too long and costly to allow simultaneous contact to all of the devices on a wafer, as required for simultaneous burn-in of all of the devices on the wafer. In addition, long cantilever wire probes are not suitable for functional testing of high-speed devices because of a high self and mutual inductance of the long, parallel wires comprising the probes.
A small, high-performance probe that can be made at low cost is required for practical application of wafer burn-in and test procedures. To be useful for wafer burn-in and test, the probes must reliably contact all of the pads on the devices under test while they are on the undiced wafer. Probes for contacting the wafer must provide electrical contact to pads on devices where the pads vary in height on the surface of the wafer. In addition, the probes must break through any oxide layers on the surface of the contact pads in order to make a reliable electrical contact to each pad. Many approaches have been tried to provide a cost-effective and reliable means to probe wafers for burn-in and test, without complete success.
A number of attempts have been tried to provide small, vertically compliant probes for contacting reliably the pads on devices on a wafer. According to the invention represented by U.S. Pat. No. 4,189,825, to David R. Robillard and Robert L. Michaels, a cantilever probe is provided for testing integrated circuit devices. In
FIG. 1
, cantilever
28
supports sharp tips
26
above aluminum contact pads
24
on a chip
23
. A compliant member
25
is urged downward to move tips
26
into contact with pads
24
. An aluminum oxide layer on pad
24
is broken by sharp tip
26
in order to make electrical contact between tip
24
and the aluminum metal of pad
24
. The rigidity of small cantilever beams is generally insufficient to apply the force to a tip that is necessary to cause it to break through an aluminum oxide layer on a contact pad, without an external means of applying force to the cantilever. Cantilever beams of glass, silicon, ceramic material, and tungsten have been tried in various configurations, without success in providing burn-in probes of sufficient force and flexibility.
A flexible membrane probe shown in
FIG. 2A
is described in Flexible Contact Probe, IBM Technical Disclosure Bulletin, October 1972, page 1513. A flexible dielectric film
32
includes terminals
33
that are suited to making electrical contact with pads on integrated circuits. Terminals
33
are connected to test electronics by means of flexible wires
34
attached to contact pads
35
on terminals
33
. Probes fabricated on a flexible polyimide sheet were described in the Proceedings of the IEEE International Test Conference (1988) by Leslie et al. The flexible sheet allows a limited amount of vertical motion to accommodate variations in height of bond pads on integrated circuits on a wafer under test. Membrane probes such as that described by Leslie et al provide connections to integrated circuit chips for high performance testing. However, dimensional stability of the membrane is not sufficient to allow contacts to pads on a full wafer during a burn-in temperature cycle.
Fabrication of the contacts on a thin silicon dioxide membrane is shown in
FIG. 2B
as described in U.S. Pat. No. 5,225,771 by Glenn J. Leedy. A silicon dioxide membrane
40
has better dimensional stability than polyimide, thereby somewhat ameliorating the dimensional stability problem of mating contacts to pads on a wafer under test. Probe tips
41
are connected by vias
44
through membrane
40
to circuit traces
45
that are linked to an additional layer of circuitry
42
above a dielectric film
43
. Limited vertical compliance of the test probes on silicon dioxide membrane
40
renders use of probe arrays unreliable for use in burn-in of devices on a semiconductor wafer.
Fabrication of an array of burn-in probes on a semiconductor wafer is described in U.S. Pat. No. 4,585,991, as illustrated in
FIGS. 3A and 3B
showing a top plan view and a sectional view respectively. Probe
51
is a pyramid attached to semiconductor wafer substrate
52
by arms
54
. Material
53
is removed from the semiconductor wafer
52
in order to isolate mechanically the probe
51
. A probes as in
FIG. 3A
provides a limited vertical movement but do not allow space on the substrate for wiring needed to connect an array of probes to test electronics required for dynamic burn-in.
An approach to providing flexible probes to device contact pads involves the use of flexible wires or posts to connect test circuitry to pads on a chip. A flexible probe shown in
FIG. 4A
is described in U.S. Pat. No. 5,977,787 by Gobina Das et al. Probe
60
is a buckling beam, generally described in U.S. Pat. No. 3,806,801 by Ronald Bove. Probe
60
is adapted for use in burn-in of devices on a wafer. Probe
60
is held by guides
61
and
62
that have a coefficient of expansion similar to that of the wafer being tested. Probe
60
is offset by a small distance
63
to provide a definite modality of deflection. Although buckling beams are well suited to testing individual integrated circuit chips, they are too expensive to be
Allen Kenneth R.
Cuneo Kamand
Decision Track LLC
Patel Paresh
Townsend and Townsend / and Crew LLP
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