Single ram multiple-delay variable delay circuit

Details Single ram multiple-delay variable delay circuit Single ram multiple-delay variable delay circuit

1994-03-16

1995-12-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327261, 365194, G11C 700

Patent

active

054791286

ABSTRACT:
A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.

REFERENCES:
patent: 4506348 (1985-03-01), Miller et al.
patent: 4549283 (1985-10-01), McDermott, III
patent: 4876670 (1989-10-01), Nakabayashi et al.
patent: 4945518 (1990-07-01), Muramatsu et al.
patent: 4953128 (1990-07-01), Kawai et al.
patent: 4961169 (1990-10-01), Matsumura et al.
patent: 5200925 (1993-04-01), Morooka
patent: 5406518 (1995-04-01), Sun et al.

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