Single rail CMOS register array and sense amplifier circuit ther

Details Single rail CMOS register array and sense amplifier circuit ther Single rail CMOS register array and sense amplifier circuit ther

1988-03-30

1989-06-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 307279, 307481, 307452, 365205, 377117, H03K 326, H03K 3284, H03K 19094

Patent

active

048374652

ABSTRACT:
A storage cell and a sense amplifier for use in a register or other memory in an integrated circuit. The storage cell has single-rail input and output, thereby eliminating the necessity of differential input lines and access transistors. The cell also has dual individually-addressable output buses. The sense amplifier includes a master latch connected to the bit line from the storage cell and a slave latch connected to the output. The master latch is normally maintained at its meta-stable condition by a normally-enabled gate. When the content of a storage cell is to be read, the cell outputs a signal onto the bit line, which signal drives the master latch to one side of its meta-stable state. The gate is turned off, allowing the master latch to go to the nearest stable state. The slave latch is connected to the master latch and assumes a state in response thereto. The slave latch and master latch are then disconnected and the master latch returned to its meta-stable state.

REFERENCES:
patent: 3983545 (1976-09-01), Curdaro
patent: 4506167 (1985-03-01), Little et al.
patent: 4551641 (1985-11-01), Pelley, III
patent: 4691122 (1987-09-01), Schnizlein et al.
patent: 4703200 (1987-10-01), Zangara
patent: 4705965 (1987-11-01), Stuyt

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