Single polycrystalline silicon memory cell

Details Single polycrystalline silicon memory cell Single polycrystalline silicon memory cell

1980-06-30

1984-09-11

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 23, 357 41, 357 51, 365154, H01L 2704, H01L 2978, G11C 1100

Patent

active

044713746

ABSTRACT:
A single polycrystalline silicone configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.

REFERENCES:
patent: 4110776 (1978-08-01), Rao et al.
patent: 4240097 (1980-12-01), Raymond, Jr.
patent: 4246593 (1981-01-01), Bartlett
patent: 4280271 (1981-07-01), Lou et al.
patent: 4322824 (1982-03-01), Allan

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