Single-poly non-volatile memory device and its operation method

Details Single-poly non-volatile memory device and its operation method Single-poly non-volatile memory device and its operation method

2008-05-22

2009-06-23

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185260

Reexamination Certificate

active

07551494

ABSTRACT:
A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+source doping region and a P+drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

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