Single poly non-volatile memory

Details Single poly non-volatile memory Single poly non-volatile memory

2007-04-24

2007-04-24

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280

Reexamination Certificate

active

10905736

ABSTRACT:
An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

REFERENCES:
patent: 4956564 (1990-09-01), Holler et al.
patent: 5294819 (1994-03-01), Simko
patent: 5604700 (1997-02-01), Parris et al.
patent: 5640344 (1997-06-01), Pani et al.
patent: 6028787 (2000-02-01), Sansbury et al.
patent: 6038190 (2000-03-01), Kowalski et al.

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