Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2000-09-15
2001-11-06
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S108000
Reexamination Certificate
active
06313678
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to voltage waveform slew rate control, commonly referred to as edge rate control, and in the preferred embodiment, to the adjustment of pulse rise and fall times for various conditions of backplane loading and operating temperature, implemented in a complementary metal oxide semiconductor (CMOS) device.
BACKGROUND OF THE INVENTION
The backplane assembly of a high speed data processing and transmission system is a primary source of potentially unacceptable electronic noise and electromagnetic interference (EMI). This may involve signals in the frequency range of 150-175 Mhz but is not necessarily confined to this frequency range. The presence of noise and/or EMI can render a high speed data system functionally inoperative by causing misinterpretation of data bits by the inclusive circuitry, resulting in high bit-error-rates or system lock-up. Another detrimental effect of system noise is to cause unwanted fluctuations in the circuit supply voltage. This is particularly undesirable when the device comprises Gunning Transceiver Logic (GTL) because a lower supply voltage, 1.2-1.5 volts vs 3.3 volts, is implemented to achieve higher processing speeds.
The backplane noise is directly proportional to the rate of change of current flowing in the backplane circuit paths with respect to time, and to the inductance of these circuit paths, or L*(di/dt). This change in current flow is inherent in digital circuits due to the amplitude change of pulse waveforms with time. Specific pulse waveform characteristics that must be focused on in order to minimize or eliminate this system noise are the pulse rise and fall times, which determine the pulse edge rate or slew rate. Further, it is desired to provide the capability to increase the rise and fall times, thereby reducing the edge rate, in order to reduce the magnitude of di/dt. It is also desired to allow faster edge rates when system noise is not a prevalent problem or can otherwise be tolerated, an example of which would be a data transmission system operating in a lower frequency range than is applicable here.
The inductance of the circuit paths is a fixed physical parameter that is derived from backplane interconnections, such as printed wiring board (PWB) connectors, and interconnect wiring within the semiconductor devices. Such inductance is minimized in the backplane and device layout design process, leaving edge rate control as the primary means of alleviating system noise.
There currently exist several techniques for reducing system noise through use of edge rate control. Representative examples are given below with appropriate references:
Edge rate feedback CMOS output buffer circuit, U.S. Pat. No: 5,121,000. This invention includes an output driver stage that is formed of a pull-up transistor, a pull-down transistor, and feedback means. The feedback means is responsive to the output signal for controlling the rate of rise of the voltage at the gate electrode of the pull-down transistor so as to slow down its turn-on time when the output terminal is making a high-to-low transition, thereby reducing the ground bounce. The feedback means is preferably formed of a capacitor having a first plate connected to the output terminal and a second plate connected to the gate electrode of the pull-down transistor.
Controlled slew rate buffer, U.S. Pat. No. 5,138,194. This invention comprises a driver receiving voltage along a voltage supply line and includes feedback apparatus which senses the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold.
CMOS driver having reduced switching noise, U.S. Pat. No. 5,241,221. This invention is comprised of a driver circuit with high- and low-impedance drive means which operate in parallel to effect a desired output transition. Adaptive control means respond to a threshold value of the output signal and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise.
CMOS buffer with controlled slew rate, U.S. Pat. No. 5,619,147. In this invention a feedback path from the output is coupled to transistors comprising a differential pair; the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback means to control the high-to-low and low-to-high transition rate of the output.
Slew Rate Controlled CMOS TIA/EIA-485 Transceiver, DS36C280, and RS423 Programmable Slew Rate Line Driver, DS9636A, National Semiconductor Corp. devices, have provisions for connecting an external resistor by the user, the value of which determines the rise and fall times of the output waveform.
SUMMARY OF THE INVENTION
An embodiment of the invention will be disclosed in the context of its use in a semiconductor device known as a data bus transceiver, comprised of Gunning Transceiver Logic (GTL), for use in backplanes utilized in high speed data communications. This invention provides the means to adjust the rise and fall times of the output waveform, or edge rate, by adjusting the voltage on a single external pin provided on the transceiver for that specific purpose. The current art does not include an edge rate control means that utilizes an external single-pin means for adjusting and controlling waveform edge rate by application of a single control voltage by the, user at the said external pin.
Further, the detailed description of the invention will show that upon application of a voltage such as VDD, which is the primary supply voltage for the bus transceiver, at the aforementioned external pin the rise and fall times of the transceiver output voltage waveform are increased significantly, causing a corresponding decrease in instantaneous circuit current, or di/dt, for the specific purpose of reducing system noise. The detailed description will also show that upon application of a lower voltage such as ground potential at the external pin the rise and fall times of the transceiver output voltage waveform are decreased significantly, for the specific purpose of allowing faster edge rates when desired by the user.
The detailed description will further show that the edge rate control circuitry of the invention utilizes two signals that originate elsewhere in the transceiver, said signals not being related to the invention. These signals are output from another transceiver circuit and change with variations in backplane process, backplane temperature, and VDD.
It will still further be shown that application of VDD at the aforementioned external pin of the transceiver causes an increase in the effective resistivity of the final drive path for the output voltage waveform, thereby reducing the drive strength to the final output transistor of the transceiver. A reduced drive strength to the output transistor causes the rise and fall times of the transceiver output voltage waveform to be significantly increased, thereby achieving a slower edge rate. It will also be shown that application of ground potential to this same external pin of the transceiver causes a decrease in the effective resistivity of the final drive path for the output waveform, thereby increasing the drive strength to the final output transistor of the transceiver. An increase in drive strength to the output transistor causes the rise and fall times of the transceiver output voltage waveform to be significantly decreased, thereby achieving a faster edge rate.
The detailed description will further show that the invention incorporates the capability to place the transceiver output in a high-output impedance state, or tristate mode, whenever necessary for proper transceiver operation or to prevent damage to the transceiver dev
Brady III Wade James
Le Dinh T.
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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