Single phase clock distribution circuit for providing clock sign

Details Single phase clock distribution circuit for providing clock sign Single phase clock distribution circuit for providing clock sign

1990-09-05

1994-04-19

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307585, 365233, 395275, G06F 104, G06F 13372, H03K 17687

Patent

active

053054512

ABSTRACT:
A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

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patent: 5107137 (1992-04-01), Kinugasa et al.
"A Method to Obtain an Optimal Clocking Scheme for a Digital System" by James Beausang et al, 1985 IEEE.

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