Single parity bit generation circuit

Details Single parity bit generation circuit Single parity bit generation circuit

1983-05-04

1985-08-27

Smith, Jerry

Excavating

G06F 1110

Patent

active

045382719

ABSTRACT:
The subject parity circuit generates a single parity bit for a prescribed DATA SET. The DATA SET comprises n bytes which are simultaneously transmitted to the parity circuit over n data transmission leads. The n bytes are simultaneously combined bit by bit to determine whether an odd or even number of bits have been received. A cummulative sum is determined, and the single parity bit is generated with the receipt of the last n bits of the DATA SET.

REFERENCES:
patent: 3487363 (1969-12-01), Wall
Hill, Introduction to Switching Theory and Logical Design, 2nd ed., 1974, p. 202, 3rd ed., 1981, pp. 241-244.
Mano, Computer Logic Design, 1972, pp. 157-159.
Grimes, IBM Technical Disclosure Bulletin, Two-Dimensional Parity Error Correction Procedure, vol. 25, No. 5, 10/82, pp. 2686-2689.

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